International Business Machines Corporation

Brian Robert Kessler

Donald Lawrence Wheater

Erik A Nelson

Thomas E Obremski

William R Corbin

Edward E Horton, Iii

Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.

Testing logic and embedded memory in parallel

A process for diagnosing test result data produced during boundary scan testing of a circuit device having a plurality of boundary scan latches at endpoints interconnected in a plurality of nets. The process identifies the particular endpoint that is defective out of all the endpoints in a defective net so that a repair can be efficiently directed to the identified endpoint. The process looks for recognizable patterns of failures in failure data resulting from each test pattern in a boundary scan test, particularly the symptom pattern of a failed endpoint that fails to drive all other endpoints on the net when acting as a driver and fails to receive data from all other endpoints when acting as a receiver.

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Lagrangeville, NY, United States of America

Brian Robert Kessler