Lockheed Martin Corporation

Sperry Corporation

Unisys Corporation

Brian Ralph Larson

Donald B Bennett

Steven Allen Murphy

Charles John Kryzak

Thomas Ormond Wolff

Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred &ldquo;layered network&rdquo; of U.S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U.S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.

Three-dimensional interconnection geometries for multi-stage switching networks using flexible ribbon cable connection between multiple planes

Dense physical and electrical connection of (i) flat flexible multiconductor cables of the printed circuit or ribbon types, to (ii) to spaced-parallel planar modules, particularly to switching modules containing switching chips, is realized by (1) a particular connection geometry in combination with (2) a spring clip connector. Flat flexible multiconductor cables routed through free space either in (i) &ldquo;X&rdquo; and, optionally also, &ldquo;Z&rdquo; planes, or else in (ii) &ldquo;Y&rdquo; planes exclusively, have their conductors' ends stripped and bent 90&deg; so as to lie upon conductive pads, arrayed along lines angled 45&deg; to both the &ldquo;X&rdquo; and &ldquo;Y&rdquo; planes, located on the substrates of switching modules that are within &ldquo;Z&rdquo; planes. A substantially square, substantially planar, spring clip mounts and re-mounts to the substrate by, preferably, two tabs fitting in a corresponding two holes in the substrate, so as to hold exposed conductor ends of each cable bent 90&deg; compressively against a portion of the arrayed conductive pads, making electrical connections.

Pad and cable geometries for spring clip mounting and electrically connecting flat flexible multiconductor printed circuit cables to switching chips on spaced-parallel planar modules

Multi-stage switching networks may be constructed and expanded from small to very large networks that are contained within a compact physical volume. This is accomplished by replication of a pre-selected network module containing switches by a rotating, folding and squaring process that substantially reduces the length of connections between switches. This geometry allows very large networks by inductively combining smaller networks into larger networks. In networks constructed with this geometry, the length of the longest connections between switches is proportional to the square root of the number of ports provided by the network.

Implementation of multi-stage switching networks

An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

Single-type fabric card networks and method of implementing same

A Layered Network system may provide varying cost from order NlogN low-cost networds, to completely-routing, fully-Layered networks with cots of order Nlog .sup.3 N. Layered networks are composed of switches and point-to-point connections between them. These networks establish connections from requestors to responders by relaying 'requests' through the switches. Each switch has built-in control logic to route requests and responses. The switch setting is determined using the comparison of the request with the request's current location in the network, and with locally competing requests. To provide distributed routing without a centralized controller, each switch routes the requests using only the information contained in the requests that switch handles. The switch setting is remembered in order to route the responses on the same paths as the associated requests, but in the reverse direction.

Layered network

A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic '1' the weight value of the input data device that supplied this '1' signal is added to the weight values of all other input data devices that supplied '1' data bits. If the data bit from a particular input device is a logic '0', then its weight is added to the weight values for other input data devices which supplied logic '0''. Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic '1' or a logic '0'. After the correct output bit is obtained, it is compared with the input bits supplied by the different input data devices, and the stoned weight values associated with each of these are decremented if the input device supplied a data bit that did not conform to the correct output bit, or alternately they are incremented if it did.

Digital adaptive voting

An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N. A final comparator stage based on exclusive OR gates and an OR gate(s) compares the X+1 signals representing the actual bit count with an equal number of binary encoded signals representing the then desired number M, M.ltoreq.N, and produces an error signal if the number of binary ones detected is not equal to M. A preferred embodiment implementation of the berger code generator circuits utilizes exclusive OR logical elements based on the CMOS technology transfer gate structure.

Growing community of inventors

Eagan, MN, United States of America

Brian Ralph Larson