Intel Corporation

Brian R Nickerson

Michael J Keith

Fernando C M Martins

Stuart J Golin

Rohan G Coelho

Christopher J Lord

Sreenath Kurupati

Jonathan W Liu

Sunil B Chaudhari

Samuel Wong

Larry E Wickstrom

Chunrong Zhu

Mohammad Ashraf Bhuiyan

A decode unit to decode an instruction that indicates a source packed data that includes data elements, and indicates a source mask that includes mask elements. Each of the mask elements corresponds to a different one of the data elements. Each of the mask elements is one of a masked mask element and an unmasked mask element. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data. When the source packed data includes one or more masked data elements disposed within unmasked data elements, the result packed data includes, the unmasked data elements consolidated together without the one or more masked data elements disposed within them. The execution unit, is to store a result in a second destination storage location that reflects a number of the unmasked data elements consolidated together.

Processors, methods, systems, and instructions to consolidate data elements and generate index updates

A method and apparatus for hardware-based anamorphic video scaling. In one embodiment, the method includes the fetch of zero or more new input pixels according to an entry of an input control memory corresponding to a current output pixel. Once fetched, the zero or more new input pixels replace at least one stored input pixel of N, input pixels. Using the updated N, input pixels and an N, coefficient set selected according to an entry of a coefficient memory corresponding to the current output pixel, a pixel computation, such as, for example, an anamorphic scaling computation, is performed. In one embodiment, the anamorphic scaling is performed by subdividing an X&#xd7;Y pixel frame into X/M M&#xd7;Y pixel subframes. Other embodiments are described and claimed.

Apparatus and method for hardware-based video/image post-processing

A method and apparatus are provided for video bit stream extension by video information annotation. In one embodiment, the invention may include gathering video data from a video source, gathering non-visual video information associated with the video data, maintaining a current state of the video information in storage, and annotating the video data with the current state of the video information.

Video bit stream extension by video information annotation

A method and apparatus are provided for annotating video and audio media with supplementary content for post video processing. In one embodiment, the invention may include maintaining a current state of auxiliary information regarding a sequence of video frames, the sequence of video frames being encoded as a video bit stream having video frame data for each respective video frame of the sequence of video frames. It may further include comparing the current state of auxiliary information with auxiliary information regarding a current video frame of the sequence of video frames to determine differential information, and annotating the differential information to the video bit stream as an annotation to the video frame data for the current video frame.

Video bit stream extension by differential information annotation

A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.

Apparatus and method for edge handling in image processing

A method and apparatus are provided for annotating video and audio media with supplementary content for post video processing. The method includes the steps of accepting video data from a video source and storing video information associated with the video data as the video data is being accepted. Then, the video information may be appended to the video data for later use in the form of annotations, for example.

Video bit stream extension with supplementary content information to aid in subsequent video processing

A method and apparatus for managing resources. The apparatus includes a pattern recognition block to receive the video signal comprising an eye image and to generate a first signal indicating an orientation of the eye image; and an operating system to manage resources depending on the first signal.

Eye tracking for resource and power management

A method for processing image data includes quantizing a region in a frame with an initial quantizer level. It is determined whether an amount of bits required for encoding the region after quantizing the region with the initial quantizer level is within a bit allocation budget. The region is re-quantized if the amount of bits is not within the bit allocation budget.

Method and apparatus for controlling video encoder output bit rate using progressive re-quantization

For each image, an initial set of quantization (Q) levels is selected based on the pixel data. The pixel data are transformed to blocks of transform coefficients. The initial set of Q levels is incremented and decremented. The incremented Q levels are used to generate a low estimate of bitrate for the transform coefficients and the decremented Q levels are used to generate a high estimate of bitrate for the transform coefficients. The low and high bitrate estimates are compared to a specified target bitrate to generate Q-level adjustments. The Q-level adjustments are used to select the Q levels to encode fully the quantized coefficients of the current image in the sequence of images.

Bitrate damper for selecting quantization levels for image encoding

An estimate of the number of bits required to encode a block of transform coefficients at a specified quantization (Q) level is generated without performing the actual encoding. The transform coefficients and the specified Q level are used to generate indices to lookup tables that map to the number of bits contributed to the encoded bitstream by each transform coefficient. lookup table may be used to perform non-linear compression to map Q level, unquantized transform coefficients, and zero runs to degrees of quantizer, unquantized coefficient, and zero run. The degrees of quantizer and unquantized coefficient are used to generate an index to another lookup table that maps to a degree of quantized coefficient. The degrees of quantized coefficient and zero run are then used to generate an index to yet another lookup table that maps to the number of bits contributed to the encoded bitstream.

Bitrate estimator for selecting quantization levels for image encoding

Image signals are converted from one color format to another using a lookup table based on interleaved indices generated from the components in the first color format. In a preferred embodiment, image signals in a YUV format are converted to image signals in a CLUT format by interleaving bits from the U and V components and appending bits from the Y component. By interleaving the U and V components, cache efficiency is improved when color conversion is implemented on a general-purpose processor with limited on-chip cache.

Table-driven color conversion using interleaved indices

Image data in an initial color format (e.g., subsampled YUV9 data) is color converted to a selected RGB16 color format by executing compiled computer program code. The same compiled computer program code can be used to convert the image data in the initial color format into image data in any of two or more different RGB16 formats. In a preferred embodiment, lookup tables (configurable during run-time processing) are used to make the color conversion processing more efficient. The selected RGB16 color format can be changed during run-time processing, in which case certain lookup tables are reinitialized for the newly selected RGB16 format.

Table-based color conversion to different RGB16 formats

A prediction block is generated using a first region of a first reference frame and a second region of a second reference frame. A current block of a current frame is compared to the prediction block, where the comparison is based on a set of match points from the current block and a corresponding set of match points from the prediction block. The current block is processed based on the comparison of the current block to the prediction block. For each match point of the prediction block, a table index is generated from a pixel of the first region and either a pixel of the second region or an offset value, and a corresponding entry is retrieved from a lookup table using the table index. The comparison of the current block to the prediction block is based on the lookup-table entries for the prediction block. In a preferred embodiment, prediction blocks are generated for motion-estimation processing for bi-directionally predicted (B) frames of certain video encoding standards such as the H.263 standard.

Table-driven bi-directional motion estimation using scratch area and

Consecutive pixel values are loaded into the fields of a register. The data stored in the register is then transformed by operating on the register with one or more instructions that treat multiple pixel values as if they were single values. In a preferred embodiment, subsampled motion estimation processing is implemented on SIMD architecture. Values for consecutive pixels are loaded into the 8-bit fields of a SIMD register with a single byte-based SIMD load instruction. The contents of the register are then processed by applying one or more word-based SIMD instructions to the register which treat the data in the registers as 16-bit values. This word-based processing preferably results in sums of squares of differences between reference and target pixels used in motion estimation processing. Although the byte-based SIMD load instruction loads unwanted pixels (i.e., those pixels not selected for subsampled motion estimation processing) along with the desired pixels, the subsequent word-based SIMD processing treats the unwanted pixels as low-order bits of the desired pixels. The squares of differences may have errors, but the magnitudes of the errors are insignificant compared to the overall block comparison values and, as such, produce negligible if any affect on the selection of reference blocks during motion estimation processing.

Growing community of inventors

Aloha, OR, United States of America

Brian R Nickerson