Ast Research, Inc.

Intel Corporation

Brian R Bennett

Stephen S Chang

Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to modify the shared resource is pending. The method further comprising retrying each subsequent nonmodifying bus transaction for the shared resource until the status bit is cleared.

Prevention of live-lock in a multi-processor system

A system for facilitating debugging of software running within an information processing unit includes an external trigger state machine which selectively overrides the cacheability attribute of a cache line. An in-circuit emulator (ICE), which is used for debugging purposes, monitors addresses read by and written to a CPU. If an address which is of interest for debugging purposes is detected by the ICE, then the ICE issues a trigger signal. The trigger signal causes the external trigger state machine to designate the cache line associated with the detected address as a non-cacheable operation (i.e., to override the cacheability attribute) . Thus, the data associated with the cache line is written out to the main memory module where the data can be observed by an ICE, rather than to an internal cache memory location where the data would be invisible to an ICE. In a preferred embodiment of the invention, the external trigger state machine is configured to operate in a pipelining environment wherein multiple requests may be outstanding at one time.

External means of overriding and controlling cacheability attribute of

A method and apparatus for interfacing multiple integrated circuit chip devices to a system bus includes higher speed portions of a circuit within a primary IC chip and lower speed portions of a circuit within a secondary IC chip. The primary IC chip connects directly to the system bus while the secondary IC chip receives the same bus signals via the primary IC chip after a one clock cycle delay. Both the primary and secondary IC chips are capable of driving signals out onto the system bus when the primary and secondary ICs are part of a bus master circuit. When the primary and secondary ICs act as bus masters, signals are received by the secondary IC chip in the same clock cycle as the primary IC chip receives the signals. Thus, the secondary IC includes a state machine to indicate if the received signals are delayed by one clock cycle or not. In a preferred embodiment, the same pins are used by the primary IC to drive signals through to the secondary IC as to drive signals out onto the system bus.

Minimum latency bus interface circuit with reduced I/O pin count through

A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring circuit which monitors the addresses requested by the local CPU. If the local CPU addresses a memory module which is different from the last accessed memory module, then the subsystem monitoring circuit initiates a request to maintain control of the system bus. In this manner, sequential write and read operations are typically made to interleaved memory modules so that the effects of module recovery time are minimized. The subsystem monitoring circuit includes a transfer count register which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus. In this manner, fair arbitration is assured for other CPUs contending for control of the system bus.

Multiprocessor system bus protocol for optimized accessing of

A system for inhibiting interrupts during posted write transfers in a computer system utilizes a buffer to store incoming data and addresses while monitoring incoming addresses to determine if the address is an Input/Output reference to an interrupt controller. If an Input/Output reference to an interrupt controller is detected, a counter is incremented which outputs a logical zero output. A signal indicating a counter value of zero is provided as an input to an AND gate. A second input to the AND gate is provided from an interrupt controller. When the counter contains a non-zero value, a zero input is provided to the AND gate and a zero output is provided to the system bus, regardless of the output from the interrupt controller, inhibiting all further interrupts. Thus, when an interrupt mask is set by a CPU, the present invention immediately inhibits further interrupts from occurring, thereby permitting processing to continue without interruption. As a result, processing time is increased.

Method and apparatus for increasing bus bandwidth on a system bus by

An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS.sub.-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.

Signaling protocol for concurrent bus access in a multiprocessor system

An improved bus architecture system for use in a multi-processor computer system has a shared address bus and a shared data bus, and has at least two separate memory modules. The system reduces the bus latency time by allowing sequential address requests to different memory modules to begin before previous cycles are terminated. Preferably, the physical memory is mapped onto several separate memory modules which will increase the probability that concurrent address requests from different processors on the common bus are for different memory modules. The processor address determines which memory module contains the data for a new request. If the memory module addressed by the new request differs from the memory module addressed by the current request, the bus controller may issue an early address request for the new data. While the early address request for the new request is being processed, the current bus cycle for the data located in the first memory module is completed on the shared data bus. Thus, the bus latency in a tightly-coupled multi-processor system can be significantly reduced using the improved bus architecture.

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Laguna Niguel, CA, United States of America

Brian R Bennett