Broadcom Corporation

Conexant Systems, Inc.

S3 Incorporated, Inc.

Exponential Technology, Inc.

Brian R Baird

Daniel Talayco

Earl T Cohen

Mohan V Kalkunte

James S Blomgren

Yuanlong Wang

Srinivas Sampath

Daniel Fu

Kevin Cameron

Gurumurthy V S Yeleswarapu

Xiaofan Wei

Zong Yu

Puneet Agarwal

Shalesh Thusoo

David E Richter

Bora Akyol

Venkateshwar Buduma

Allan Christie

David M Stark

The invention provides a method and system for communication between processors. Rather than provide an external network connection solely for providing a communication link between CPUs, the present invention utilizes the network devices to transfer information between CPUs. A transmitting network device marks a control packet, which is intended as a communication between CPUs, as control traffic. The receiving network device will determine whether the received control packet is intended for its own CPU and provide the control packet to its CPU if that is the case.

Method for communication between processors

Methods and network device apparatus for discovering interconnections between a plurality of network devices are disclosed. An example network device apparatus includes a first stack port configured to couple the network device with a next network device and a second stack port configured to couple the network device with a previous network device. The example network device is configured to send, to the next network device through the first stack port, a first probe packet and a routing packet. The example network device is further configured to receive, from the previous network device through the second stack port, a second probe packet and the routing packet. The example network device is still further configured to confirm that the previous network device and the next network device have received configuration information included in the routing packet.

Dynamic connectivity determination

A method, system and apparatus for constructing dispatch tables match application program interface service routines. The invention includes reading a header file of the application program interface. The invention further includes generating a corresponding dispatch table for at least one device indicated in the header file, wherein the corresponding dispatch tables are generated based on information read from the header file. The invention further includes verifying that the information contained in the dispatch tables is consistent with current requirements of the application program interface.

API interface to make dispatch tables to match API routines

The invention includes a method system and apparatus for an asynchronous event notification. In the event that a system-wide application requires notification of an asynchronous event that occurs in a remote device within the communications system, the event is locally detected and the necessary information is forwarded to the application.

Asynchronous event notification

A method, system and apparatus for decoupling devices in a network for use by a system-wide application. The invention includes accumulating configuration information for the network, wherein the network includes a plurality of units, and each of the units includes a processor and at least one switch device. The invention further includes analyzing the configuration information and determining a logical configuration for the network based on the analyzed configuration information. The invention further includes virtually attaching a remote switch device to the network.

Virtual system configuration

A method and system for automatically trunking ports connecting network devices arranged in a stacked configuration is provided. The method includes sending a packet, from a sending network device to at least one other receiving network device, through each of a plurality of ports of the network device. The packet includes at least an identifier for identifying the sending network device. The receiving network device maintains a table identifying which ports are connected to a neighboring network device. The network device automatically trunks the ports which are connected to the same network device.

High speed autotrucking

A method of adjusting fields of a datagram in the handling of the datagram in a network device may comprising receiving a datagram, with the datagram having at least module identifier fields and port identifier fields, at a port of a network device, adding or subtracting an offset value to at least one of the module identifier fields and at least one of the port identifier fields of the datagram based on data registers in the network device, and forwarding the datagram to a legacy device based on the module and port identifier fields of the datagram. A size of each of the module identifier fields and the port identifier fields handled by the legacy device may be smaller than a size of the module identifier fields and port identifier fields handled by the network device.

Remapping module identifier fields and port identifier fields

Methods and systems for processing packets in data network using multistage classification are disclosed. An example method for processing packets includes receiving a data packet at a first processing stage and examining the packet at the first processing stage to determine a first attribute of the packet. Based on the first attribute, a first classification is assigned to the packet. In the example method, the packet and the first classification are communicated from the first processing stage to a second processing stage and the packet is examined at the second processing stage to determine a second attribute of the packet. Based on the second attribute, a second classification is assigned to the packet. The example method further includes processing the packet based on the first classification and the second classification.

Network packet processing using multi-stage classification

A method of adjusting fields of a datagram in the handling of the datagram in a network device is disclosed. The method includes receiving a datagram, with the datagram having at least module identifier fields and port identifier fields, at a port of a network device, determining whether the received datagram is a unicast datagram, adjusting the module and port identifier fields of the datagram based on data registers in the network device when the received datagram is a unicast datagram and forwarding the datagram based on the module and port identifier fields of the datagram. The port of the network device is connected to a legacy device, where the legacy device has a reduced handling capacity when compared to the network device.

Method and apparatus for remapping module identifiers and substituting ports in network devices

A method and system for discovering interconnections between a plurality of network devices arranged in a stacked configuration is provided. A probe packet, including a tag indicating a transmit port from which the probe packet was transmitted and a receive port at which the probe packet was received, is sent from one network device to a next network device. A routing packet is sent from each of the network devices, including information regarding the configuration of the stack of network devices. A master network device is elected. The master network device sends a topology packet, which includes final configuration information, to the other network devices.

High speed autotrunking

A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both bus-based based and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.

Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both busbased and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.

A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.

Debug and video queue for multi-processor chip

A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The upper portion of the target address, its block number, which corresponds to the starting address of a 2K block, is generated from the target finder simply by taking the upper portion or block number of the branch instruction and incrementing and decrementing it, and using the block encoding in the finder to select either the unmodified block number of the branch instruction, or the incremented or decremented block number of the branch instruction. The lower portion of the target address that was stored in the finder is concatenated with the selected block number to get the predicted target address. The target address can be predicted in parallel with reading an instruction out of the cache, making the target available at the same time the branch instruction is available, eliminating pipeline stalls for correctly predicted branches. The initially predicted target address in the finder is generated by a quick decode of the instruction and is written when the cache is loaded from memory. The initial prediction does not have to be accurate because branch resolution logic will update the finder on each branch resolution. Register indirect branches and exceptions may also be predicted. Two instruction sets may be accommodated by different block encodings to indicate the instruction set. By using the block encoding, the finder array is small and inexpensive.

Growing community of inventors

Pleasanton, CA, United States of America

Brian R Baird