Analog Devices,inc.

Massana Research Limited

Lsi Corporation

Analog Devices International Unlimited Company

Brian Paul Murray

Timothy J Cummins

Colm J Prendergast

Christian Willibald Bohm

Philip A Curran

Albert Molina

Carl Murray

Philip Curran

Michal Brychta

Luis De La Torre Vega

Vincent Berg

Jacobo Riesco-Prieto

Jose Rodriguez

Christopher Bleakley

Disclosed are embodiments that provide digital data communication between a single-pair Ethernet and a multi-pair Ethernet. Some embodiments include a single-pair Ethernet interface that is configured to operate in at least two modes. In a first mode, the single-pair Ethernet interface operates in a conventional manner. In a second mode, alternate pin configurations are employed to provide a low-cost interoperability between a single-pair Ethernet interface and a multi-pair Ethernet interface. For example, in the second mode, the single-pair Ethernet receives, via a first receive data pin, from a first transmit data pin of the multi-pair Ethernet interface, a data signal, and receives, via a second receive data pin, from a second transmit data pin of the multi-pair Ethernet interface, a second data signal.

Single-pair to multi-pair ethernet converter

A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog front ends is operative to perform signal conversion between a digital domain and an analog domain. The physical layer device further includes a digital switching circuit coupled to the digital core and to the first and second analog front ends. The digital switching circuit is operative to electrically connect the digital core to the first analog front end or the second analog front end as a function of a control signal applied to the digital switching circuit.

Physical layer interface for computing devices

A cancellation system comprises a channel circuit () for each noise source, such as echo in a particular cable pair. There are only eighty taps per channel, in two blocks (n_echo_a, f_echo_a). Each block is preceded by a variable delay line comprising blocks of registers cascaded so that a delay value of 0 to 40 clock cycles can be chosen. The delay value is determined by determining an optimum position for each tap block. This is achieved by determining a maximum coefficient sum for a number of windows. Taps from other channels are used during training, so that there is a total of 160 taps for each channel during training to enable the optimum positions to be determined.

Echo and crosstalk cancellation

An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU ( ) has a register file ( ) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) ( ) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU ( ), selection multiplexers ( ) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix- operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder ), and the least significant bits (LSBs) are taken from the output of a second adder (adder ) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder. The DSP includes a program control unit for delivering a control signal to the AGU for selection of a required addressing operation.

Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations

A comb filter for use in a video decoder is described. The comb filter includes a line memory for storing as successive pairs of U and V samples of a decoded video signal corresponding to a previous horizontal line of video information and a line memory for storing a second previous horizontal line of video information. The filter also includes a circuit to calculate an average value of both U and V from a previous sample and a corresponding sample from a previous line. The filter also includes a circuit for calculating a correction term for each one of the averages. The correction term is calculated from the opposite color component as was used to calculate the average value.

Adaptive comb filter that cancels hugand cross-luminance errors

A digital-to-analog video encoder method and apparatus having unique equalization are disclosed. The encoder converts digital video signals into one or more analog video formats using one or more digital-to-analog converters. Equalization is provided to compensate for zero order hold effects of the digital-to-analog converters. Equalization is provided to a luminance signal and/or a chroma signal to equalize RGB, composite video, and super VHS video outputs. Multiplexed digital-to-analog converter inputs allow selection of several output formats.

Digital-to-analog video encoder with novel equalization

A novel finite impulse response filter apparatus and method. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operates are connected to and odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.

Method and apparatus for time shaped finite impulse response filter with

A video decoder is provided wherein digitized samples of an input video signal are produced at a fixed sampling rate and, from such digitized samples, a fixed number of re-sampled digitized samples are produced for each detected sync pulse included in the video signal. The re-sampled digitized samples are stored in a buffer memory and are retrieved from such buffer memory at a rate synchronized to the sync pulse. With such an arrangement, the analog to digital converter operates at a fixed sampling rate, and overflow situations are avoided.

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Dublin, Ireland

Brian Paul Murray