Cypress Semiconductor Corporation

Brian P Evans

Jeffery Scott Hunt

Anup Nayak

Andrew J Wright

James Daniel Merchant

Gordon Carskadon

Roland T Knaack

Benjamin J Bowers

An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

Configurable matrix architecture

A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy

An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.

Push/pull multiplexer bit

An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.

Layout architecture to optimize path delays

A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.

Method and system for identifying configuration circuit addresses in a schematic hierarchy

The present invention provides a circuit and method for generating a parity bit and checking the parity of data words positioned in the read data path of a memory device or buffer. The parity check mode can detect errors. The parity generation mode generates EVEN or ODD parity as an additional bit. Other devices in the system may generally be configured to accept either EVEN or ODD parity. The parity generation and checking circuit can detect errors in both the data input to the buffer as well as errors created in the storage of the data by the buffer.

Growing community of inventors

Starkville, MS, United States of America

Brian P Evans