Nortel Networks Corporation

Rockstar Consortium US LP

Brian Neil Baker

Terry E Newell

Ruth Beyerlein

Barry Wood

Gregory Waines

Robert LaRiviere

Sylvain Joseph Henri Chenard

Guy Mousseau

Bing L Wong

A method for routing input/output () data in a telecommunication system including a network node having a plurality of first integrated circuit (IC) cards, a plurality of second IC cards and a switching fabric, each second IC card connected to a corresponding first IC card in a respective slot of the network node xs described. The method involves receiving the IO data at an external port of any of the plurality of first or second IC cards. When packets of the IO data are received at an external port of a given second IC card, the given second IC card performs a packet classification of the packets to at least in part determine a destination for the packets. A further step of the method includes delivering the packets to a first or second IC card destination according to the packet classification performed by the given second IC card via a logical network layer existing on the first and second IC cards and the switching fabric. A particular implementation includes use in an Advanced Telecommunication Computing Architecture (ATCA) system.

Methods and systems for providing a logical network layer for delivery of input/output data

A method and system for containing a fault in a network node. A loss of all remaining communication links from a node is detected. A time duration from the loss of a first remaining communication link to the loss of a last remaining communication link is determined. It is established that the node has contained a fault when the time duration for the loss of the first remaining communication link to the loss of the last remaining communication link is not more than a predetermined amount of time.

Method and system for telecommunication apparatus fast fault notification

A high availability computing system having multiple processing elements capable of simultaneous execution of multiple software programs and seamless software upgrades is disclosed. The system comprises multiple processing elements, each processing element capable of accessing memory at processing element memory addresses; and multiple memory modules each having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined address space. The system further includes a memory element interface in communication with each of the memory elements permitting alteration of the defined address space for the memory element. An address mapper is interconnected between each of the processing elements and at least one of the memory elements. The address mapper is capable of mapping a processing element memory address to a global memory address within a defined address space. Thus, the system may allocate memory addresses used by a single one of the memory elements to an address space used by only a single processing element. The system further has access ports to each of the memory elements, thus allowing the single processing element limited access to other memory modules. Conversely, other processing elements may have limited access to the single memory module. As a result, the single computing system may be divided into two logical computing systems. Software upgrades may be loaded into one system, without interrupting the other system.

High availability computing system

The present invention relates to a method and apparatus for ensuring fault detection and system recovery in a multiprocessor computing system. This system comprises a multitude of processing element modules, input/output processor modules and shared memory modules. Each module within the system includes an identical period sanity timer capable to reset the module once a predetermined limit count is reached. If a global clear signal is not received from the operating system scheduler by all modules prior to the expiry of the sanity timers, a system-wide reset is effected. Each processing element module within the system further includes a watchdog timer capable to reset the module once a predetermined limit count is reached. If a process is not run by the operating system scheduler on the processing element before the expiry of the watchdog timer, effectively clearing the watchdog timer, the processing element is reset and removed from service.

Method and apparatus for ensuring proper functionality of a shared memory, multiprocessor system

A method and apparatus for receiving status information from shared logical memory modules in a computer system including redundant memory. The status information includes whether the shared logical memory modules are in a transitional state and the number of logical memory modules in the mirror set. When shared logical memory modules are added or removed from redundant memory they go through a transitional state when the memory card may respond to a request for data held on the card, but that data may be unreliable. Checking this status information allows better error checking of data and fault detection of the shared logical memory module.

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Dunrobin, Canada

Brian Neil Baker