Vlsi Technology, Inc.

Brian N Fall

Philip Wszolek

Barry M Davis

Swaroop Adusumilli

Rodney J Pesavento

James C Steele

Nicholas Julian Richardson

David K Cassetti

Nick Richardson

David R Evoy

Franklyn H Story

Joseph Alan Thomsen

W Henry Potts

Hrushikesh Nalubola

Richard Demers

A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data items to a write buffer in a bridge circuit which are to be sent out on a device bus, such as a PCI bus. When the CPU writes a data item to the shared memory after writing a data item to the write buffer, a dirty bit is set for each location in the write buffer that stores a data item. When a bus device requests access to the shared memory, the dirty bits are checked. If the dirty bits are set, the bus device is denied access to the shared memory to maintain write coherency. When bus device access is denied, the bus device is informed to retry its request at a later time, and data items in the write buffer are flushed to devices on the bus. The write buffer is disabled after flushing the data items so that the CPU cannot write additional data items to the write buffer until the bus device has retried and accessed the shared memory.

Method and apparatus for maintaining coherency for data transaction of

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Method and apparatus for direct access to main memory by an I/O bus

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

Method and apparatus for arbitrating access to main memory of a computer

A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit. There is further included second circuit for determining whether the PCI slave is still able to complete the PCI-MEMORY transaction. Additionally, there is included third circuit for asserting an asynchronous handshake acknowledge signal to cancel the CPU-PCI transaction and removing the deadlock condition if the PCI slave is unable to complete the PCI-MEMORY transaction.

Deadlock resolution methods and apparatus for interfacing concurrent and

A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.

Computer bus mastery system and method having a lock mechanism

A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

Apparatus for granting either a CPU data bus or a memory data bus or a

A serial bus Input/Output (I/O) system has multiple I/O devices which are all connected in daisy-chain fashion on a serial bus. These I/O devices service peripherals that may generate different interrupt requests or DMA requests to the system controller. These requests are encoded, serialized and transmitted to the system controller on the serial bus, allowing the system controller to service a large number of interrupt requests and DMA requests via the serial bus with a very small number of external pins.

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Chandler, AZ, United States of America

Brian N Fall