Siemens Aktiengesellschaft

Brian Murphy

Martin Zibert

Dominique Savignac

Dieter Gleis

An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source. The MOS-transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS-transistor is conducting.

CMOS buffer circuit with controlled current source

An integrated buffer circuit configuration has two inverters which are mutually connected in series. The first inverter includes an n-channel transistor and a constant current source. The source of the n-channel transistor is connected to a first supply potential. The drain of the transistor is connected with the constant current source through a first enable transistor. A second enable transistor is connected parallel to the constant current source. The gates of enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS transistor may function as the constant current source. The MOS transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS transistor is conducting.

MOS output buffer circuit with controlled current source

A CMOS buffer circuit includes a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source. A first n-channel MOS transistor is connected in series with the p-channel MOS transistor and has a source terminal connected to a reference potential and a drain terminal connected to an output terminal. A second n-channel MOS transistor is connected between and in series with the p-channel MOS transistor and the first n-channel MOS transistor. The second n-channel MOS transistor has a gate terminal connected to the pump voltage source.

CMOS buffer having output terminal overvoltage-caused latch-up protection

An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.

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Brombach, Germany

Brian Murphy