International Business Machines Corporation

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Brian Mitchell Bass

Michael Steven Siegel

Marco C Heddes

Fabrice Jean Verplanken

Jean Louis Calvignac

Anthony Matteo Gallo

Piyush Chunilal Patel

Edward Hau-chun Ku

Gordon Taylor Davis

Clark Debs Jeffries

Michael Raymond Trombley

Loren Blair Reiss

James Johnson Allen, Jr

Antonios Maragkos

Ross Boyd Leavens

Douglas Ray Henderson

Joseph M Rash

Scott J Lemke

Bartholomew Blaner

Sridhar Rao

Santosh Prasad Gaur

Brian Alan Youngman

Jeffrey Haskell Derby

Norman Clark Strole

Mark Anthony Rinaldi

Joseph Gerald McDonald

Kenneth Harvey Potter, Jr

Steven Kenneth Jenkins

George William Daly, Jr

Hubertus Franke

Giora Biran

Thuong Quang Truong

Ravinder Kumar Sabhikhi

Kenneth Anthony Lauricella

Hao Yu

Thomas Eric Ryle

Price Ward Oman

Rama Mohan Yedavalli

Frank J Pita

Jitesh Ramachandran Nair

Robert William Bartoldus

James Allison Hubbard

Guy L Guthrie

Derek E Williams

William John Starke

Charles Ray Johns

Charles Steven Lingafelt

Lakshminarayana Baba Arimilli

Colin Beaton Verrilli

Hugh Shen

Bernard Charles Drerup

David James Shippy

Eric Francis Robinson

Ronald Nick Kalla

Juan Guillermo Revilla

Amit Golander

Robert Dov Herzl

Kenneth James Barker

Joseph Kinman Lee

Sonia Kiang Rovner

Jeffrey James Lynch

David W Cummings

Edward Joel Rovner

Thomas L Jeremiah

Brahmanand Kumar Gorti

Chad Everett Winemiller

Jay Gerald Heaslip

Jim Philip Ervin

Dennis Albert Doidge

Samuel Steven Allison

Peter Irma August Barri

Gail Irene Woodland

Miroslav Vrana

Scott Nellenbach

Loren Douglas Larsen

Metin Aydemir

Jack S Chorpenning

Teresa Lynn Davis

William Craig Troop

Jeffrey Wayne Kidd

Karen Park Heron

Sidney Brower Schrum, Jr

Ivan Oscar Clemminck

Timothy Droz

Simin H Sanaye

Bou-Chung Lin

A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines

A system and method of terminating processing requests dispatched to a coprocessor hardware accelerator in a multi-processor computer system based on matching various fields in the request made to the coprocessor to identify the process to be terminated. A kill command is initiated by a write operation to a coprocessor block kill register and has match enable and value for each field in the coprocessor request to be terminated. Enabled fields may have one or more values associated with a single request or multiple requests for the same coprocessor. At least one match enable must be set to initiate a kill request. A process kill active signal prevents other coprocessor jobs from moving between operational stages in the coprocessor hardware accelerator. Processing jobs that are idle or do not match the fields with match enables set signal done with no match and continue processing. Processing jobs that do match the fields with match enables set are terminated and signal done with match. When all processing jobs have signaled done, a done bit is set in the coprocessor block kill register to indicate completion of the kill to the initiating software. The register also holds the match status of each processing job.

Termination of requests in a distributed coprocessor system

A structure and method of allocating read buffers among multiple bus agents requesting read access in a multi-processor computer system. The number of outstanding reads a requestor may have based on the current function it is executing is dynamically limited, instead of based on local buffer space available or a fixed allocation, which improves the overall bandwidth of the requestors sharing the buffers. A requesting bus agent may control when read data may be returned from shared buffers to minimize the amount of local buffer space allocated for each requesting agent, while maintaining high bandwidth output for local buffers. Requests can be made for virtual buffers by oversubscribing the physical buffers and controlling the return of read data to the buffers.

Managing access to shared buffer resources

Techniques for replacing one or more blocks in a cache, the one or more blocks being associated with a plurality of data streams, are provided. The one or more blocks in the cache are grouped into one or more groups, each corresponding to one of the plurality of data streams. One or more incoming blocks are received. To free space, the one or more blocks of the one or more groups in the cache are invalidated in accordance with at least one of an inactivity of a given data stream corresponding to the one or more groups and a length of the one or more groups. The one or more incoming blocks are stored in the cache. A number of data streams maintained within the cache is maximized.

Maintaining a cache of blocks from a plurality of data streams

A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.

Processor system and methods of triggering a block move using a system bus write command initiated by user code

A method for decompressing multiple data streams includes receiving a packet of data of a compressed data stream, directing the received packet to a selected one of a plurality of decompression functional units within a hardware-based decompression accelerator unit, obtaining decompression state information pertaining to the compressed data stream, and decompressing the received packet using the obtained decompression state information.

Method and apparatus for concurrent and stateful decompression of multiple compressed data streams

The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.

Retro flow control for arriving traffic in computer networks

Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires 'n' number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

Longest prefix match (LPM) algorithm implementation for a network processor

A memory subsystem includes Data Storeand Data Store. Each data store is partitioned into N buffers, N&#x3e;1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Storeand a second buffer from Data Store, while a second format selects a first buffer from Data Storeand a second buffer from Data Store. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.

Balanced bandwidth utilization

A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.

Combined response cancellation for load command

An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.

Network switch and components and method of operation

A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.

The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.

Distributed address arbitration scheme for symmetrical multiprocessor system

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Apex, NC, United States of America

Brian Mitchell Bass