International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Marvell Asia Pte., Ltd.

Other

Brian Michael Rogers

Ken Van Vu

Ganesh Balakrishnan

Srinivasan Ramani

Andrew D Hilton

Mohammad Peyravian

Robert Allen Shearer

Hans Mikael Jacobson

Miguel Comparan

Alfred T Watson, Iii

Waseem Kraipak

Eric Francis Robinson

Anil Krishna

Jason Alan Cox

Gordon Bernard Bell

M V V Anil Krishna

Pradipkumar Arunbhai Thaker

Timothy Hume Heil

Monty Montague Denneau

Deepak K Singh

Kenichi Tsuchiya

Mvv Anil Krishna

A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss comprises providing a page fetch/walk logic module disposed between a coherent fabric and a memory controller. Upon receiving a notification of a TLB miss, performing, by the page fetch/walk logic module, a page table walk of a virtual address to produce a corresponding physical address. The method may further comprise forming, by a memory management unit, a TLB request that comprises a virtual address, and a request type field. The request type field may comprise (i) an indication that a TLB miss has occurred and (ii) a specification of a number of stages required of the page table walk.

Innovative way to improve the translation lookaside buffer (TLB) miss latency

A hardware-based compaction accelerator may comprise two or more decoders, a merge iterator, a compaction module, and an encoder. Each of the decoders converts a sorted string table (SST) files into a corresponding key-value (KV) format data stream. The merge iterator receives a KV format data stream from each of the decoders, and combines the KV format data streams into a single KV format data stream. The compaction module receives the composite KV format data stream and produces a compacted data stream. The compacted data stream contains less data that is in the composite KV format data stream. The encoder converts the composite KV format data stream back into one or more output SST files. The compaction accelerator may be configured to perform only a subset of the processing available from the decoders, merge iterator, compaction module, and encoder, and may be configured through the Internet using a cloud-based processor.

Method and system for performing a compaction/merge job using a merge based tile architecture

Disclosed is a method of recovering corrupted data, comprising providing a FIFO storage structure on the memory controller, and providing an error correction code (ECC) generator to the memory device, the ECC generator configured to generate ECC check bits based on a data word. For each data word, the method comprises storing a copy of the data word, appended check bits, and associated address into the FIFO storage structure; generating expected check bits based on the data word; when the expected check bits match the appended check bits, storing the data word and appended check bits to the memory device; and when the expected check bits do not match the appended check bits, and an error in the data word is uncorrectable, replacing the data word and appended check bits with the copy of the data word and appended check bits that were stored in the FIFO storage structure.

Mechanism for improved data availability for DRAM in the presence of uncorrectable errors

A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Application-level signal handling and application-level memory protection

A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Managing servers with quality of service assurances

Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n&#x2212;1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Carry-less population count

A method for managing processor power optimization is provided. The method may include receiving a plurality of tasks for processing by a processor environment. The method may also include allocating a portion of a compute resource corresponding to the processor environment to each of the received plurality of tasks, the allocating of the portion being based on both an execution time and a response time associated with each of the received plurality of tasks.

Processor power optimization with response time assurance

Branch prediction for indirect jumps, including: receiving, by a branch prediction module, a branch address for each of a plurality of executed branch instructions; receiving, by the branch prediction module, an instruction address of a current branch instruction; creating, by the branch prediction module, an execution path identifier in dependence upon the branch address for each of the plurality of executed branch instructions and the instruction address of the current branch instruction; and searching, by the branch prediction module, a branch prediction table for an entry that matches the execution path identifier.

Branch prediction for indirect jumps by hashing current and previous branch instruction addresses

Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.

Growing community of inventors

Durham, NC, United States of America

Brian Michael Rogers