International Business Machines Corporation

Globalfoundries Inc.

Suss Microtec Photonic Systems Inc.

Brian Michael Erwin

Charles Leon Arvin

Brian W Quinlan

Thomas Weiss

Wolfgang Sauter

Eric D Perfecto

Mark William Kapfhammer

Charles L Reynolds

Gary William Maier

Nicholas A Polomoff

Ekta Misra

George John Scott

Jennifer D Schuler

Jeffrey P Gambino

Ian D Melville

Grant W Wagner

David Michael Audette

Harry David Cox

Christopher Lee Tessler

Dennis R Conti

Karen P McLaughlin

Chris Muzzy

Matthew E Souter

Yuri M Brovman

Timothy Harrison Daubenspeck

Christopher David Muzzy

Jae-Woong Nah

David John Russell

Jon Alfred Casey

Thomas Anthony Wassick

Steven Paul Ostrander

David Lewis Gardell

Sarah Huffsmith Knickerbocker

James N Humenik

Rajneesh Kumar

Jorge A Lubguban

Clement J Fortin

John Lawson

At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.

Formation of terminal metallurgy on laminates and boards

An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Integrated circuit tester probe contact liner

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Carrier and integrated memory

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

Finned contact

An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Element place on laminates

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

Method of forming a temporary test structure for device fabrication

A method of making a security mesh comprises forming on a conductive substrate an alumina film having through-holes in which metal, e.g., copper, through-wires are formed. First surface wires are formed on one surface of the alumina film and second surface wires are formed on the second, opposite surface of the alumina film in order to connect selected through-wires into a continuous undulating electrical circuit embedded within the alumina film. The security mesh product comprises an alumina film having a continuous undulating electrical circuit comprising copper or other conductive metal extending therethrough. A stacked security mesh comprises two or more of the mesh products being stacked one above the other.

Security mesh and method of making

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

Substrate including selectively formed barrier layer

Growing community of inventors

Lagrangeville, NY, United States of America

Brian Michael Erwin