Hewlett-packard Development Company, L.p.

Brian Matthew Johnson

Mark A Shaw

Mark Edward Shaw

Richard A Schumacher

Roy M Zeighami

Stuart C Haden

John A Nerl

Michael C Day

Vicki L Smith

David Glen Edwards

June E Goodwin

Gregg Bernard Lesartre

Gary Belgrave Gostin

Craig William Warner

Guy Lowell Kuntz

Bryan Stephenson

Paul Bouchier

Richard Dickert Powers

Rajakrishnan Radjassamy

John M Wastlick

Todd J Kjos

Vipul Gandhi

Brendan A Voge

David Soper

Ryan Lee Weaver

Brad O Underwood

Glen Edwards

Kevin A Egan

Ronald J Bellomlo

Leon Hong

D Glen Edwards

Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Apparatus for configuring I/O signal levels of interfacing logic circuits

A system comprises plural electronic modules, at least one interconnect structure and plural power supplies. The electronic modules communicate over the interconnect structure. The system further comprises plural redundant manager modules to perform management tasks with respect to the at least one interconnect structure and the power supplies.

Redundant manager modules to perform management tasks with respect to an interconnect structure and power supplies

A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Memory module with a predetermined arrangement of pins

A method and system for correcting errors in a memory subsystem in a computer system. Occurrence of correctable memory errors are monitored and a determination is made whether the risk of an occurrence of an uncorrectable memory error is less than a tolerable risk. If the risk of an occurrence of an uncorrectable memory error is not less than the tolerable risk, at least one system level parameter is adjusted to decrease the occurrence of correctable memory errors.

Method and system for performing system-level correction of memory errors

One embodiment is a method of dynamically adjusting a rate at which a dynamic random access memory ('DRAM') module is refreshed in a computer system. The method comprises monitoring a plurality of system conditions; detecting a change in at least one of the monitored system conditions; responsive to the detection, determining an optimum refresh rate for a current state of the computer system; and setting the refresh rate to the determined optimum refresh rate.

Method and system for dynamically adjusting DRAM refresh rate

One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

Double-high DIMM with dual registers and related methods

A partitionable computer system and method of operating the same is disclosed. The partitionable computer system has a state machine, a processor, and a device controller. The state machine can be configured to monitor the status of a partition of the partitionable computer system. The information provided by the state machine can be used to provide security within the partitionable computing system.

Security measures in a partitionable computing system

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Allen, TX, United States of America

Brian Matthew Johnson