Data General Corporation

Brian Martin

Michael Tehranian

Robert W Beauchamp

Jonathan Shapiro

Brian Milas

Michael Giancioppo

Paul D Linton

Brian Gruttadauria

Sheldon P Gringorten

A device access controller residing in a first computer system for transferring virtual inputs and outputs representing operations of the first system between the first system and a second system. The device access controller includes a video controller for performing video display operations, a video memory for storing video data representing operations of the first system, a network controller for transferring information between the first system and the second system, a controller processor, and a device access controller bus interconnecting the video controller, the network controller and the processor. A video interface is connected between the first system bus and the device access controller bus for receiving video information including video data and video write addresses from the first system bus and into the video memory and controller and the controller processor and network controller are responsive to the writing of video data into the video memory for reading the video information including the video data from the video memory and the video data write addresses from the video controller registers and transmitting the video information including the video data and the video data write addresses to the second system. The device access controller further includes a keyboard interface, a disk interface, and a serial interface operating in manners generally analogous to the video interface for corresponding communicating corresponding data between the first and second systems.

Device access controller for virtual video/keyboard/mouse input/output

A BIOS address decoder for addressing an extended BIOS memory for storing additional microprograms in a computer system. A system component is connected from the bus for receiving program instruction addresses in a first address range and providing corresponding BIOS memory addresses in a corresponding first BIOS address range. The BIOS address decoder includes the system component to receive a first subset of bus address bits representing bus addresses in the first instruction address range and responsive to the first subset of bus address bits to generate corresponding BIOS addresses in the first BIOS address range and a BIOS address indication indicating that the first subset of bus address bits indicates a bus address in the first instruction address range. An extended BIOS decoder is connected from the bus to receive a second subset of bus address bits representing bus addresses including an extended instruction address range and from the system component to receive the BIOS address indication output and is responsive to the second subset of bus address bit and the BIOS address indication for generating an extended BIOS memory enable output having a first state when the second subset of bus address bits does not represent a bus address including the extended instruction address range and a second state when the second subset of bus address bits represent a bus address including the extended instruction address range.

BIOS memory address decoder for providing an extended BIOS memory

A support facility for installation of interprocessor unit cabling interconnecting the processor units of a multiple processor unit system in a first network, including a second system for directing the cabling interconnections of the first system and, in each processor unit of the first system, a device access controller connected through a second network to a second system, each device access controller including a memory for storing a unique identifier, and a network controller to interconnect to a network controller of at least one other processor unit. There is a selectably settable anchor bit indicator to indicate a processor unit selected as a first processor unit of the first network, a next connection indicator connected from the device access controller, and connected from the network controller, a transmit test indicator connected from the device access controller and a receive indicator connected from the device access controller. The second system identifies the units of the first system and directs a user through the cable interconnections of the first network.

Device access controller and remote support facility for installation of

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Worcester, MA, United States of America

Brian Martin