Texas Instruments Corporation

Brian M Trentman

Freidoon Mehrad

Brian Keith Kirkpatrick

Shashank Sureshchandra Ekbote

Deborah J Riley

Zhihao Chen

Clint Montgomery

James B Friedmann

Troy A Yocum

Juanita DeLoach

Shangting Detweiler

Randall W Pak

A silicon rich anti-reflective coating () is formed on a layer () in which narrow linewidth features are to be formed. Prior to the formation of a photoresist layer (), the anti-reflecting coating () is exposed to excited oxygen species to reduce photoresist poisoning.

Method to reduce photoresist poisoning

A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

Protection of silicon from phosphoric acid using thick chemical oxide

Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Shallow trench isolation structure and method

The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etchingthrough a patterned hardmask layerlocated over a semiconductor substratewherein the plasma etching forms a modified layeron the hardmask layer, and removing at least a substantial portion of the modified layerby exposing the modified layerto a post plasma clean process.

Post plasma clean process for a hardmask

In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

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Sherman, TX, United States of America

Brian M Trentman