Motorola Corporation

Brian M Spinks

Stanley E Groves

Rodney J Means

Gene A Schriber

Thomas C Daly

Richard M Baker

John R Dumas

A sense amplifier having a conventional three transistor network for charging a column to a first predetermined voltage uses a depletion transistor to charge the column beyond the first predetermined voltage for detection of a memory cell which is in a non-conducting state. A memory cell in a conducting state draws enough current to prevent the depletion transistor from charging the column beyond the first predetermined voltage. A logic '1' is detected when the column charges beyond the first predetermined voltage to at least a second predetermined voltage, whereas a logic '0' is detected when the column does not reach the second predetermined voltage.

Sense amplifier

An MOS logic circuit is provided which generates and latches an output signal at a given logic level upon detection of a given transition in an input signal coinciding with a given state of a clock signal. The circuit utilizes the capacitance inherent in an MOS structure. The circuit requires a minimum of MOS components and is therefore useful in high density MOS integrated circuits where it is desired to detect and latch a transition in a signal. The edge sense latch comprises an MOS inverter (Q1, Q2) responsive to an input signal S, a transmission gate (Q3) controlled by a clock signal, a transmission gate (Q4) controlled in part by an inherent capacitance (29), a latch comprising a pair of cross-coupled MOS transistors (Q5, Q8) for generating an output signal Q, and an MOS transistor (Q6) responsive to a reset signal R.

Edge sense latch

A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch. Reset circuitry resets the counter whenever the 16-bit latch is written into, and the counter counts until it reaches the number written into the 16-bit latch, whereupon the interrupt circuitry generates an interrupt signal and sets an appropriate interrupt bit in the status register, and also resets that counter. The counter continues counting at the appropriate clock rate after the interrupt so that time since the interrupt may be determined by the microprocessor. The outputs of the three counters can be selected as outputs of the programmable timer module.

Growing community of inventors

Austin, TX, United States of America

Brian M Spinks