Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Motorola Corporation

Brian M Millar

Ahsan Habib Chowdhury

William C Moyer

Michael D Fitzsimmons

Andrew Paul Hoover

Suhail Ahmed

John M Fedor

Prashant U Kenkare

John J Vaglica

Matthew S Berzins

Frank P Helms

Michael C Lewis

Michael I Catherwood

Milind P Padhye

Yohan Kwon

Rajesh Rajagopalan Kashyap

Linda R Nuckolls

Jinkyu Lee

Robert A Colyer

Tom Andre

According to one general aspect, a method may include receiving a digital circuit model. The digital circuit model may include models of a clock mesh configured to provide a clock signal to a plurality of logic circuits, and a plurality of logic circuits, each logic circuit at least partially controlled by an application of the clock signal to one or more clock-gater cells. The method may include identifying a group of clock-gater cells having common input signals. The method may include calculating at least one clustered sub-portion of the group of clock-gater cells based upon a set of bounding dimensions, wherein each clustered sub-portion includes a plurality of clock-gater cells. The method may further include, for each clustered sub-portion, de-cloning in the digital circuit model the clock-gater cells by reducing the clock-gater cells to a new clock-gater cell and replacing the each clock-gater cell with a matching buffer cell.

Power savings method in a clock mesh-based design through a smart decloning technique

Embodiments of the inventive concept include a computer-implemented method for intelligently swapping circuit cells and an associated intelligent cell swapper logic section. The technique can include receiving, by an intelligent cell swapper logic section, a synthesized gate level netlist including cells each having an initial cell class. A cell class sorter can sort cell classes in order of leakage. A ceiling finder can swap the initial cell class for each of the cells to a highest cell leakage class, and determine a ceiling frequency. A floor finder can swap the highest cell leakage class for each of the cells to a lowest cell leakage class, and determine a floor frequency. An effective swap weight calculator section can determine an effective swap weight for a subset of cells based on cell attribute weighting criteria. The timing paths can be optimized to meet the ceiling frequency without unnecessarily using high leakage cells.

Intelligent cell swapping based on ceiling determination, floor determination, and cell attribute weighting criteria

According to one general aspect, a method may include receiving a digital circuit model that includes models of a clock mesh and a plurality of logic circuits, each logic circuit associated with end-points of the logic circuit. The method may also include identifying a cluster of end-points, wherein the cluster is associated with a common version of the clock signal. The method may also include identifying an associated skew-schedule for each end-point. The method may include determining a timing slack and skew schedule for each end-point within the cluster. The method may include adjusting a clock-gater cell, based upon a common push/pull schedule associated with the cluster. The method may further include inserting, for at least one end-point of the cluster, a skew-buffer, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the end-point's skew schedule and the common push/pull schedule.

Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design

According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage of the first power signal. The apparatus may include a first electrical circuit configured to be powered by the first power supply. The apparatus may also include a power mode controller configured to: determine the voltage of the first power signal during the next power state, and generate a selector control signal based upon the voltage of the first power signal. The apparatus may also include a power supply selector configured to dynamically electrically couple a second electrical circuit with either the first power signal or the second power signal, based upon the selector control signal.

Dual supply memory

According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model.

Efficient skew scheduling methodology for performance and low power of a clock-mesh implementation

An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Integrated circuit with a programmable delay and a method thereof

In one embodiment, a data processing system () has a processor () coupled to a bus, where the data processing system () includes access error detection circuitry () and access error response circuitry (), each coupled to the bus (). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value () or a predetermined data value (). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.

Method and apparatus for responding to access errors in a data processing system

Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.

Low power system and method for a data processing system

A flip-flop () has a normal mode and a low power mode to save power. The flip-flop () has a master latch () and a slave latch (). The slave latch () is used to retain the condition of the flip-flop () during the low power mode, where power is withdrawn from the master latch () but maintained on the slave latch (). The slave latch () may use transistors with lower leakage characteristics than the transistors that make up the master latch (). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop () is maintained by implementing the slave latch () so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch () has an input/output terminal to tap into the signal path between the master latch and an output circuit ().

Flip-flop circuit having low power data retention

A memory controller portion of a DRAM is synchronized to a system clock, while an array portion of the DRAM is allowed to process signals at the array's natural frequency&mdash;independent of fixed timing parameters. By allowing the array portion to function at its natural frequency, the array's performance is not limited to &ldquo;worst case&rdquo; parameters; instead the DRAM can achieve maximize array performance at all voltage and temperature corners. The controller portion of the DRAM initiates an array access cycle, then waits until the array portion returns a data-valid signal. Since the array portion of the DRAM operates at its own natural frequency the data-valid signal can be completely asynchronous to the controller portion of the DRAM, which is operating in synchronization with a system clock. In order to ensure that the data-valid signal is latched properly, the controller sends an early version of the system clock to the data valid circuitry in the array portion of the DRAM. This early version of the system clock, known as the clock lockout signal, is used to effectively synchronize the output of the array portion to the controller portion, and thereby to the system clock.

Memory having a synchronous controller and asynchronous array and method thereof

A data processing system (10) having address pins (30), data pins (31), control pins (32), chip select pins (33), and other pins (34). For bus cycles of an instruction which do not require use of an external address bus (35), the values driven by the address pins (30) are 'frozen' in their previous logic state. The previous logic state is determined by the most recent value driven by address pins (30) during a bus cycle that required use of the external address bus (35). Data pins (31) may be 'frozen' in the same manner as address pins (30). Control pins 32, chip select pins 33, and other pins 34 may be driven to their respective inactive logic states. The goal is to reduce noise and power consumption by reducing the voltage level switching taking place on external conductors (35-39).

Growing community of inventors

Austin, TX, United States of America

Brian M Millar