Intel Corporation

Other

Sk Hynix Nand Product Solutions Corp.

Brian M Leitner

Dominic J Gasbarro

Tom E Burton

Dean Stuart Susnow

Mark A Schmisseur

Michael T Klinglesmith

Bradley A Burres

Sivakumar Radhakrishnan

Eric Dahlen

Pankaj Kumar

Thomas M Slaight

Sin Sim Tan

Geetani R Edirisooriya

Marc Tim Jones

David C Lee

Matthew R Wilcox

Kenneth C Haren

Saptarshi Mondal

Richard D Reohr, Jr

Balaji Parthasarathy

Ni Jie

Jie Ni

Brian M Collins

Ken C Haren

Lee Albion

Dick Reohr

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Presentation of direct accessed storage under a logical drive model

A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

Device to receive, buffer, and transmit packets of data in a packet switching network

Packet sequence numbers of request packets and response packets of transactions transferring data to or from a network interface are tracked. For every request packet transmitted by the network interface, the packet sequence number of the packet is written to a location in a circular send queue pointed to by a write pointer and a valid bit at the location is set. The write pointer is incremented if the packet is a read request packet. Alternatively, a read indicator at the location in the circular send queue pointed to by the write pointer is cleared if the packet is not a read request packet. For every response packet received by the network interface, the packet sequence number of the response packet is checked against the packet sequence number stored at the location in the circular send queue pointed to by the read pointer of the circular send queue.

Memory utilization in a network interface

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise a Micro-Engine (ME) arranged to establish connections and support data transfers via a switched fabric; a host interface arranged to receive and transmit host data transfer requests, in the form of descriptors, from the host system for data transfers, and incorporated therein a host interface Hardware Assist (HWA) mechanism configured to pre-process host descriptors for descriptor format errors in parallel with descriptor fetches so as to offload the Micro-Engine (ME) from exclusively checking for descriptor format errors; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfers; and a first-in/first-out (FIFO) interface arranged to receive and transmit data packets to/from the switched fabric via the serial interface, and incorporated therein a Protection Index and Offset Hardware Assist (HWA) mechanism configured to process the Virtual Address (VA) and Memory Handle (MH) of data packets and generate therefrom a Protection Index (PI) and Offset so as to offload said Micro-Engine (ME) from exclusively processing data packets for data transfers.

Host-fabric adapter having hardware assist architecture and method of connecting a host system to a channel-based switched fabric in a data network

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise a Micro-Engine (ME) arranged to establish connections and support data transfers via a switched fabric; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfers; a host interface arranged to receive and transmit host data transfer requests, in the form of descriptors, from the host system for data transfers; a Receiver Header Hardware Assist (HWA) Mechanism configured to check header information of incoming data packets host descriptors for header errors so as to offload the Micro-Engine (ME) from having to check for header errors; and a Transmitter Header Hardware Assist (HWA) Mechanism configured to generate OpCode and Length fields for an outgoing data packet when an entire data packet is being assembled for transmission, via the serial interface, so as to offload the Micro-Engine (ME) from having to build all data packets for data transfers.

An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.

Method and apparatus for address translation pre-fetch

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine arranged to establish connections and support data transfer operations, via a switched fabric, in response to work requests that cause instructions in a form of work queue elements 'WQES' posted from a host system for said data transfer operations; and a work queue element 'WQE' hardware assist &#x201c;HWA&#x201d; mechanism arranged to determine the starting address of each work queue element &#x201c;WQE&#x201d; based on queue pair (QP) context information needed for said Micro-Engine (ME) to process work requests for said data transfer operations.

Host-fabric adapter having work queue entry (WQE) ring hardware assist (HWA) mechanism

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfer operations via a switched fabric; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfer operations; a host interface arranged to receive and transmit host data transfer work requests from the host system for data transfer operations; a context memory arranged to provide context information necessary for data transfer operations; a doorbell manager arranged to update the context information needed for the Micro-Engine (ME) to process host data transfer requests for data transfer operations; and, a remote key manager arranged to manage remote keys and check the validity of the remote keys which correspond to outstanding data transfer operations.

Methodology and mechanism for remote key validation for NGIO/InfiniBand&#x2122; applications

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a micro-controller subsystem configured to establish connections and support data transfers via the switched fabric, and a serial interface which provides an interface with the switched fabric. The micro-controller subsystem includes a Micro-Engine (ME) which executes a ME instruction to send source and destination addresses during a control cycle, and interface logic blocks which supply addressed data from designated sources to the Micro-Engine (ME) at the same time for execution of the ME instruction during a data cycle subsequent to the control cycle.

Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in a data network

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and transmit data from said switched fabric; a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via the switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from the host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via the serial interface, and to begin working on a different task without waiting for the corresponding host response of the host request from the host interface; a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and a Request Comparator arranged to check the current VI that is being worked on by the Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to the Scheduler depending upon whether the request VI number is currently being worked on by the Micro-Engine (ME).

A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.

Growing community of inventors

Hillsboro, OR, United States of America

Brian M Leitner