Digital Equipment Corporation

3Dlabs Inc., Ltd.

Digital Corporation

Dynamic Pictures, Inc.

Brian M Kelleher

Thomas C Furlong

Shu-Shia Chow

Thomas E Dewey

Zahid Hussain

A scalable graphics processor architecture is disclosed in accordance with the present invention. In a first aspect, the architecture comprises a base graphics architecture. The architecture further includes an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture. In a second aspect, the architecture comprises a plurality of rendering processors, a first bus coupled to the plurality of processors for providing I/O signals to the processors; and a plurality of digital to analog converters (VDACs). In this aspect, each of the VDACs are adapted for driving a display. The architecture further includes a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; and a switch, coupled to a plurality of processors. The switch selectively drives the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and the rendering processors drive all of the plurality of VDACs when the switch is in a second mode. Through the use of this architecture, the graphics processor system is expandable to allow more rendering processors to be added as well as allowing the processors to drive multiple VDACs or drive a single VDAC together.

Scalable graphics processor architecture

A parallel-processor graphics architecture appropriate for multimedia graphics workstations that is scalable to the needs of a user. The graphics architecture includes one or more rendering processors and a graphics memory that is partitioned into blocks. Noncontiguous groups of the blocks are then assigned to different processors. The parallel-processor graphics architecture is scalable by the number of rendering processors utilized, and is configurable with respect to the allocation of the groups of the blocks to specific rendering processors.

Parallel-processor graphics architecture

A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). The graphics processor (48) is connected by 120-bit graphics bus (50) to frame buffer (52). The frame buffer (52) is connected to a video digital to analog converter (DAC) (54) by bus (56). The DAC (54) is connected to video display (58) by line (60). The graphics processor (48) use a technique known as super-sampling to combat the effects of aliasing. In aliased mode, the graphics processor (48) use 16 array sites to sample 16 pixels (72). When drawing a polygon or line in antialiased mode, the graphics processor (48) uses the 16 sites to sample at 16 locations (120) within a single pixel (72). The antialiasing is done by determining what proportion of the locations (120) within each pixel (72) are within the polygon and setting a color of each pixel (72) on the basis of the proportion.

System and method for drawing antialiased polygons

A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40). When the buffer (47) is full, the CPU (32) tells the graphics subsystem (45), via a read from an I/O address on the graphics subsystem (45), that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem (45) parses the packet and executes the appropriate operations atomically.

System and method for atomic access to an input/output device with

A method is provided for generating pixel color information for use in producing an image of a line segment on a graphics display screen, the method comprising the steps of: denoting at least one planar region of the display screen that encompasses the line segment; assigning respective intensity values for at least three selected pixels encompassed by the at least one planar region; assigning respective color values for the at least three selected pixels; and interpolating respective final color values for each respective pixel encompassed by the at least one planar region based upon the respective assigned intensity values and the respective assigned color values.

Method and apparatus for drawing lines in a graphics system

Method for simultaneous initialization of a double buffer and a frame

A graphics data processing system memory is allocatable by software between system memory and graphics framebuffer storage. The memory comprises two-port elements connected in parallel from the RAM port to a controller connected to a bus, and having serial output ports connected to output circuitry to map the storage to a display. Corresponding locations, relative to element origin, in all elements are addressed in parallel as an array. Three modes of memory transactions are all accomplished as array accesses. First, a processor reads/writes the system memory portion by a combination of parallel array access and transfers between controller and bus in successive bus cycles. Second, the controller executes atomic graphics operations on the framebuffer storage using successive array accesses; third, the processor can read/write a framebuffer pixel, by an array access of framebuffer storage with masking of unaddressed pixels. An interface arbitrates among requests for memory access.

Software configurable memory architecture for data processing system

A method for drawing a convex geometric figure to framebuffer storage uses a plurality of update arrays which tile the framebuffer, each having a determined origin with respect to the framebuffer. Each update array has a multiplicity of concurrently updatable pixel storage sites, each specified by an offset from array origin. A figure is specified by a set of directed segments which form its perimeter. To access only those update arrays which tile the figure, the following methodology is used. A first update array which is known to be part of the figure is accessed. Tests are then performed to find whether the figure extends to arrays above or below the accessed array. If so, the array address is stored and marked for either or both extensions. In one embodiment, a test is performed for left extension, and the steps are repeated until no further left extension is found. Returning to the initial array, the steps are repeated for right extension to complete the horizontal subset. The array marked for either up or down extension of the figure is next accessed and the steps are repeated with respect to the indicated vertically adjacent array until no further extension is found in that vertical direction; the steps are then repeated for the other vertical direction. Using this method, the figure is efficiently tiled without duplicating access to any update arrays and without accessing any update arrays that do not tile the figure.

Growing community of inventors

Palo Alto, CA, United States of America

Brian M Kelleher