Koninklijke Philips Corporation N.v.

Vlsi Technology, Inc.

Nxp B.v.

Brian Logsdon

Lonnie Calvin Goff

Subramanian S Meiyappan

Franklyn H Story

Ken Jaramillo

David R Evoy

Mark Eidson

Gabriel R Munguia

Edward Michael Petryk

A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a task ID memory.

Hardware register access via task tag ID

A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block.

Method and system for controlling internal busses to prevent bus contention during internal scan testing

Among the embodiments of the present invention is test equipment ( ) to test an integrated circuit ( ). The integrated circuit ( ) includes one or more processors and one or more communication devices ( ). The test equipment ( ) includes a responder integrated circuit ( ) that has at least one processor, several communication devices ( ), and one or more configuration connections ( ). The responder integrated circuit responds to commands from the first integrated circuit ( ) and a configuration established with the one or more configuration connections ( ) to test operation of the one or more communication devices ( ).

Multi-environment testing with a responder

A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. A bus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block. Alternatively, a centralized test device controller is used to disable the output of the second functional block, as opposed to using the grant signals of the bus arbiter. This allows the incorporation of the implementing logic without altering the logic of the bus arbiter.

Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource

A keyboard controller for a computer system with integrated Real Time Clock (RTC) functionality. The keyboard controller has a microprocessor for controlling peripheral device bus traffic such as keyboard and mouse traffic. The microprocessor also acts as a boot device for the computer system. By programming the microprocessor to emulate RTC functions, adding a divider circuit, and having an I/O support block which stores RTC registers and an extended CMOS RAM memory block, the entire RTC FSB along with its power detection and switching circuit can be removed.

Keyboard controller with integrated real time clock functionality and

A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.

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Glendale, AZ, United States of America

Brian Logsdon