Prime Computer Inc.

Brian Lefsky

Joseph L Ardini, Jr

Paul K Rodman

Stephen S Corbin

Michael Schwartz

Mary E Natusch

Robert Allison

Barbara J Farr

A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.

High availability cache organization

A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

Clock skew avoidance technique for pipeline processors

A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary. An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.

Memory control system

Methods and apparatus for accurately measuring propagation delay through very high speed VLSI devices with a test instrument having errors comparable to the delays being measured. The VLSI device has a plurality of parallel operational signal paths, each with a very short propagation delay. The VLSI device is fabricated with control circuitry for selectively connecting the parallel operational signal paths in series in a test mode so as to define a test signal path comprising multiple operational signal paths. The test signal path has a relatively long propagation delay which can be measured with acceptable accuracy by the test instrument. The test signal path is defined so that it bypasses clocked circuit elements on the VLSI device. Since the operational signal paths are on the same integrated circuit and have very well correlated operating characteristics, the propagation delay through the test signal path is a good representation of the integrated circuit dynamic operation. When the integrated circuit is not in the test mode, the series connections are disabled and the parallel circuits operate in their normally intended manner. A minimum of circuitry is added to the VLSI device in order to implement the test mode.

Method and apparatus for high accuracy measurment of VLSI components

A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

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West Newton, MA, United States of America

Brian Lefsky