Intel Corporation

Brian Leete

John I Garney

John S Howard

Brad W Hosler

Olga Adamovsky

Remi Laudebat

Eduard Kvetny

Richard L Coulson

Guy M Therien

Shahar Porat

Yuval Bachrach

Siva Ramakrishnan

Francis Corrado

Reed D Vilhauer

Yuval Elad

Sriram Ranganathan

Andrew Grover

Zeev Oster

Carl I Green

An apparatus of a Bluetooth low energy (BLE) device is provided for decreasing awake time of a host by receiving and processing peripheral data along a sideband channel and waking the host upon an event of interest, the apparatus comprising circuitry configured to receive BLE GATT data from a BLE core along a sideband channel, process the BLE GATT data, monitor processed BLE GATT data for an event of interest, and send a notification of a detection of the event of interest to the host.

Bluetooth low energy devices, systems, and associated methods

Techniques for powering up a wireless power receiving device are described herein. An example computing device includes a power receiving unit to wirelessly receive power from a power transmitting unit. The platform hardware includes a System on a Chip (SoC), a multicomm device, and a power sequence manager. The multicomm device is for wireless communication with two or more communication standards. One of the communication standards is used as a side channel for communicating with the power transmitting unit. The power sequence manager component manages activation of platform components of the platform hardware during a low battery cold boot condition. Upon detecting wireless power, the multicomm device is configured to automatically activate and the power sequence manager component is to suppress activation of other platform components of the platform hardware.

Powering up a wireless power receiving device

According to an embodiment of the invention, a method and apparatus for computer memory power backup are described. According to one embodiment, a memory system includes a first memory; a second memory coupled to the first memory and to a host, the second memory to transfer data between the first memory and the host; and a backup power source, the backup power source providing power to the first memory and the second memory if a main power source fails.

Computer memory power backup

Disclosed herein are methods that may be implemented in a mobile computer system. An exemplary method may include initiating a split of a storage volume of the mobile computer system. The storage volume may comply with a fault tolerant storage technology. Suitable technologies include, but are not limited to, those based on Redundant Array of Independent (or Inexpensive) Disks (RAID). In one aspect, the initiation of the split of the storage volume may be based, at least in part, on power availability. Then, a reduction of a power consuming state of a first storage device of the volume may be initiated.

Management of data redundancy based on power availability in mobile computer systems

A method and system to detect an occurrence of a predetermined event within the system, and change a power state of a hard drive (HD) in response to the event, are described. In one embodiment, in response to detecting consecutive HD reads have been satisfied by a non-volatile cache (NVC) of the HD, for at least a predetermined period of time, or detecting that a predetermined quantity of consecutive HD reads have been satisfied by the NVC, spinning down the HD. In an alternative embodiment, in response to detecting a predetermined number of HD data transactions have been serviced by the NVC or the HD, canceling a planned spinning down of the HD or spinning up the HD.

Method and system to change a power state of a hard drive

A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

Method and apparatus for high throughput short packet transfers with minimum memory footprint

A temperature sensitive memory, such as a ferroelectric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In such case, the system is ready for shutdown without the loss of critical data.

Adaptive cache algorithm for temperature sensitive memory

A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors where split-isochronous transaction descriptors are supported.

Apparatus for period promotion avoidance for hubs

A method and apparatus for generating, initializing, and scheduling of two interrupt queue heads to represent a single endpoint are described. In an embodiment, a method includes generating primary and secondary interrupt queue heads to represent a single interrupt endpoint. The method further includes initializing the primary and secondary interrupt queue heads. The method also includes scheduling the primary and secondary queue heads in immediately subsequent frames.

Method and apparatus for dual queue head processing of interrupt endpoints

A device is presented including a host controller to generate a transaction schedule. The transaction schedule includes many transactions. The transactions are stored in many data structures. Each of the data structures contain initialized transactions or initialized and non-initialized transactions. The host controller executes the transactions that are initialized and the data structures each contain a pointer to the next initialized transaction.

Method and apparatus for iTD scheduling

An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor, determining a current state for a transaction based on the transaction descriptor, and preventing the transaction from starting if the current state indicates the transaction has not already started.

Apparatus and method to allow and synchronize schedule changes in a USB enhanced host controller

A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.

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Beaverton, OR, United States of America

Brian Leete