Memc Electronic Materials, Inc.

Brian Lawrence Gilmore

Larry W Shive

Lance G Hellwig

Puneet Gupta

A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring.

Wafer support ring

A wafer boat for a semiconductor wafer includes vertical rods, fingers supported by the vertical rods, and plates supported by the fingers. The plate has a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

Low thermal mass semiconductor wafer boat

A support for a semiconductor wafer includes a plate having a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

Low thermal mass semiconductor wafer plate

A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Process for annealing semiconductor wafers with flat dopant depth profiles

Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.

Methods for producing smooth wafers

Low thermal mass semiconductor wafer support

Processes for the purification of silicon carbide structures, including silicon carbide coated silicon carbide structures, are disclosed. The processes described can reduce the amount of iron contamination in a silicon carbide structure by 100 to 1000 times. After purification, the silicon carbide structures are suitable for use in high temperature silicon wafer processing.

High purity silicon carbide structures

Method for purifying silicon carbide coated structures

A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.

Process for metallic contamination reduction in silicon wafers

A wafer boat for use in heat treatment of semiconductor wafers in a vertical furnace comprises support rods extending generally vertically when the wafer boat is placed in the vertical furnace. Fingers are supported by and extend along vertical extent of the support rods. Wafer holder platforms are adapted to be supported by groups of fingers lying in generally different common horizontal planes. The fingers are adapted to underlie the wafer holder platforms and support the platforms at the support locations. The fingers and wafer holder platforms each have a respective first overall maximum thickness. The support location of at least one of the fingers and the wafer holder platforms have a second maximum thickness less than the first overall maximum thickness.

Growing community of inventors

Allen, TX, United States of America

Brian Lawrence Gilmore