Qualcomm Incorporated

Altera Corporation

Brian L Wong

Geert Arnout Awater

Bruce B Pedersen

Vincent Knowles Jones, Iv

D J Richard Van Nee

Shankar Sinha

Ting Lu

Shih-Lin S Lee

Alok Shreekant Doshi

Yun Sum Wong

Partho Pratim Mishra

Wei Zhang

Albert Van Zelst

Abhishek B Sharma

Abhishek Bankey Behari Sharma

Geert A Atwater

Arnold Liu

An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.

Techniques for protecting security features of integrated circuits

An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.

Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.

Memory elements with stacked pull-up devices

This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol providing multiple frame formats to achieve delivery of one type of message with a reduced latency and other messages at increased latencies. Further, although the master initiates reads, the slave circuit may signal the master in real time over the TSI.

Systems and methods for serial communication

Integrated circuits may have arrays of memory elements. Data may be loaded into the memory elements and read from the memory elements using data lines. Address lines may be used to apply address signals to write address transistors and read circuitry. A memory element may include a bistable storage element. Read circuitry may be coupled between the bistable storage element and a data line. The read circuitry may include a data storage node. A capacitor may be coupled between the data storage node and ground and may be used in storing preloaded data from the bistable storage element. The read circuitry may include a transistor that is coupled between the bistable storage element and the data storage node and a transistor that is coupled between the data storage node and the data line.

Static random-access memory having read circuitry with capacitive storage

Systems and methodologies are described that provide low-complexity soft-output detection for MIMO communication systems. Looping can be performed over a set of constellation points per spatial stream to obtain distance metrics for each of a series of transmitted streams, for which values for the other transmitted streams can be estimated using a MIMO channel matrix and a sub-optimal MIMO algorithm. Examples of MIMO algorithms that can be utilized include Per-Stream List Detection (PSLD), Lattice-Reduced Detection (LRD), and a Guided-M Algorithm. Performance can be further improved by pre-processing the MIMO channel matrix and/or by utilizing techniques for Enhanced Metric Usage (EMU).

Near soft-output maximum-likelihood detection for multiple-input multiple-output systems

A MIMO receiver is provided with a preprocessor for performing QR decomposition of a channel matrix H wherein the factored reduced matrix R is used in place of H and Q*y is used in place of the received vector y in a maximum likelihood detector ('MLD'). The maximum likelihood detector might be a hard-decision MLD or a soft-decision MLD. A savings of computational complexity can be used to provide comparable results more quickly, using less circuitry, and/or requiring less consumed energy, or performance can be improved for a fixed amount of time, circuitry and/or energy. Where the MLD uses approximations, such as finite resolution calculations (fixed point or the like) or L1 Norm approximations, the reduced number of operations resulting from using the reduced matrix results in improved approximations as a result of the finite resolution operations. Other methods of reducing the channel matrix might be used for suitable and/or cumulative advantages.

MIMO receiver using maximum likelihood detector in combination with QR decomposition

In a packet detector, one or more tests are performed for packet detection according to packet detection parameters associated with the one or more tests, a rate of false detection is measured, and the packet detection parameters are adjusted accordingly to reduce the rate of false detection. The rate of false detection might be determined by analyzing post-detection and processing of a signal deemed to be a signal representing a packet for a failure of decoding indicative of a false detection. Such analysis might include testing for a failed SFD search, training symbol anomalies, poor conditioning of metrics used to determine frequency offset and OFDM timing, incorrect data fields, or the like.

Growing community of inventors

Pleasanton, CA, United States of America

Brian L Wong