International Business Machines Corporation

Advanced Micro Devices Corporation

Brian L Tessier

Effendi Leobandung

Wesley Charles Natzle

Louis DeWolf Lanzerotti

Ryan Wayne Wuthrich

Marc Waine Cantell

Siddhartha Panda

Huilong Zhu

David Louis Harame

Huicai Zhong

James Stuart Dunn

Byeong Yeol Kim

David M Dobuzinsky

Stephen Arthur St Onge

Ying Li

Munir D Naeem

Ricky S Amos

Robb Allen Johnson

Amanda L Tessier

Bryant C Colwill

Dureseti Chidambarrao

Shreesh Narasimha

Richard Stephan Wise

John Christopher Arnold

Rajeev Malik

A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

Field effect device with reduced thickness gate

Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator ('SOI') layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion.

Method of forming a guard ring or contact to an SOI substrate

A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

Semiconductor device structure having low and high performance devices of same conductive type on same substrate

A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator ('SOI') substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may share an edge with an SOI layer of the substrate. Desirably, a dielectric layer is deposited over a top surface of the conformal layer and the trench isolation region. A second opening can then be formed which extends through the dielectric layer and the first opening in the conformal layer. Desirably, portions of the bulk semiconductor region and the top surface of the conformal layer are exposed within the second opening. The second opening can then be filled with at least one of a metal or a semiconductor to form a conductive element contacting the exposed portions of the bulk semiconductor region and the top surface of the conformal layer.

Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Poly filled substrate contact on SOI structure

Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.

Self-aligned dual stressed layers for NFET and PFET

Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.

Undercut and residual spacer prevention for dual stressed layers

The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

Diffused extrinsic base and method for fabrication

A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

MOSFET device with in-situ doped, raised source and drain structures

Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures

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Poughkeepsie, NY, United States of America

Brian L Tessier