Honeywell Information Systems Inc.

Brian L Stoffers

John J Bradley

Theodore R Staplin, Jr

Melinda A Widen

Ming T Miu

George M O'Har

Thomas C O'Brien

A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping leading zeroes before the highest order non-zero bit of the binary number, and only allocating enough memory storage bits to hold the resultant decimal number. A multiplexer is used to apply a partial sum during conversion concurrently to both inputs of an adder for doubling.

Apparatus and method for converting a number in binary format to a

A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is apparatus utilizing a programmable memory and logic circuits that are used to subtract two operands and to generate and temporarily store a digit equal nine indication when the result of subtracting the two operands has a value of nine.

Equal nine apparatus for supporting absolute value subtracts on decimal

Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performance of the decimal multiplication, the leading zeroes prefixing the highest order significant digit in both a multiplier and a multiplicand are identified, counted and removed. Decimal multiplication is then performed using the stripped multiplier and multiplicand, and to the resultant partial product a number of zeroes are prefixed equal to the number of zeroes originally stripped from the multiplier and multiplicand. The result is the product of the original multiplier and multiplicand.

Apparatus for performing simplified decimal multiplication by stripping

What is disclosed is apparatus making up an arithmetic logic unit and utilizing a programmable read-only memory (PROM) to perform arithmetic functions for an associated processor. The PROM is used as a look-up table for computation results. Operands used to perform a mathematical computation make up an address to the PROM which is used to read out the computation result stored therein. Also stored in the PROM as part of each computation result are information bits indicating if the computation result is a valid answer. These bits are also read out and stored in flip-flops to indicate to the processor if the computation result is valid or invalid.

Arithmetic logic unit with outputs indicating invalid computation

A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is an arithmetic logic unit (ALU) that functions with the CPU. The ALU has operand inputs to which are connected switched steering circuits that permit particular operands and zero operands to be selectively applied to any or all of the ALU operand inputs. This allows easy performance of special arithmetic functions such as adding a decimal operand to itself when converting the decimal operand to a binary operand, and to subtract a decimal operand from zero when complementing decimal operands.

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No. Billerica, MA, United States of America

Brian L Stoffers