Sun Microsystems, Inc.

Apple Inc.

Open Tv Corporation

Brian L Smith

Jyh-Ming Jong

James Ray Lewis

Tai Quan

Jurgen M Schulz

Leo Yuan

Prabhansu Chakrabarti

Wai Fong

Jue Wu

Drew George Doblar

Michael J Grubisich

David J Broniarczyk

Wayne F Seltzer

Jordan Silver

Andrew Clayton

Ashok Singal

Cecilia T Chen

A method and mechanism for enabling access to a protected register in a client. A system including multiple clients, such as components and devices, is coupled to a service processor which is configured to manage the system. Clients which are managed by the service processor include control and status registers which are protected from access by unauthorized entities. Access rights for particular registers may be restricted to only the service processor. Clients include a timer which the service processor periodically updates. In the event communication is lost between the service processor and a client, the timer is not updated. In response to detecting the timer was not updated, the client is configured to alter the access rights of the register in order to permit an alternate entity to access the protected register. The service processor may then utilize the alternate entity as a proxy in order to transfer the client state to another client and configure the affected client out of the system.

Control status register access to enable domain reconfiguration

A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Automated calibration of I/O over a multi-variable eye window

A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees out of phase with the received clock signal. A second clock signal is generated to be in phase with the received source synchronous clock signal. The second clock signal is the utilized to select a newly generated clock signal and latched data for transmission in a source synchronous manner. The device is further configured to shift the phase of the generated first clock signal to be approximately ninety degrees out of phase with the received data signal.

Source synchronous I/O bus retimer

A system for testing a synchronous link utilizing a single test pattern sequence. Components coupled via a link are each configured to generate and check test patterns according to a single repeated test pattern sequence. Test patterns which are generated are based upon two simple patterns. Each test cycle, a bit is chosen from one of the two patterns for use in generating the test pattern. A sixteen cycle test pattern sequence is utilized in which values are chosen from one or the other of the two patterns in a predetermined manner. In a bi-directional test, two components which are coupled via a link alternate driving selected values based upon the predetermined sequence. Each component may alternate driving sequences of one or more cycles. An ordering of cycles may be chosen to test various permutations of driver interaction between the respective components.

IBIST test for synchronous lines at multiple frequencies

A method and mechanism for detecting interconnect and bridge defects. Contact points in a chip are assigned placement designation such that no two adjacent points have the same designation. A transmitter, receiver, and optional transmitter/receiver test are then run. During the transmitter test, transmitters with a given designation drive a particular test pattern while other transmitters drive a different test pattern. Receivers compare received test patterns against expected patterns. During a receiver test, transmitters drive a test pattern corresponding to the placement designation of the receivers to which they are coupled. During a particular receiver test, transmitters coupled to receivers of a given designation drive a particular stream, while other transmitters drive a different stream. Receivers then compare received streams against an expected stream. Finally, the placement designation of a transmitter or receiver of an adjacent transmitter/receiver pair may be temporarily assigned an alternate designation. A transmitter or receiver test is then run and receivers check received test patterns against expected patterns.

IBIST interconnect and bridge fault detection scheme

A method and mechanism for observation, testing, and diagnosis with scan chains. A device under test is configured to support scan chains. The device includes multiple blocks, each of which are configured to be individually tested with separate scan chains. Each block is configured to recirculate the scan output of its block back into its scan chain during the cycles in which it is not being directly scanned out of the chip. As the scan clock is pulsed N cycles and another block of the chip is scanned out, the recirculated state of the block will shift within the block N positions. By keeping track of the scan chain lengths of each of the blocks in the chip, and the order in which they are scanned, a determination may be made as to which element of the scan chain will be shifted out of the next block to be scanned. Further, by knowing the length N of the scan chain of a particular block and the number of cycles M it has been recirculated, the scan chain may be shifted (M % N) cycles to return the block to its originally ordered state before scanning it out.

Scan of chip state from a hierarchical design

A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Source synchronous bus repeater

An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

History FIFO with bypass wherein an order through queue is maintained irrespective of retrieval of data

A method and mechanism for testing communication links. A transmitter contact, or transmission point, is assigned a unique identifier. During a given test, the transmitter conveys a test pattern to a receiver via a link. Following this test pattern, the transmitter transmits a bit of its unique identifier to the receiver. The receiver receives both the test pattern and the identifier bit, and determines whether the received test pattern matches an expected value. If the test pattern was correctly received by the receiver, the receiver transmits the received identifier bit back to the transmitter. However, if the received test pattern is not correct, the receiver complements the received identifier bit and transmits the complemented bit back to the transmitter. The transmitter receives the identifier bit from the receiver and determines whether it matches the identifier bit which was originally transmitted by the transmitter. If the returned identifier bit does not match what was originally transmitted, the transmitter records an error.

Ibist identification loopback scheme

A method and mechanism for arbitrating and transmitting data. A first transaction and a second transaction are detected. The first transaction is targeted to a first domain and the second transaction is targeted to a second domain different than the first domain. Subsequent to receiving the transactions, arbitration domains corresponding to each are determined. In response to detecting the arbitration domains are not equal, the first and second transaction may be transmitted concurrently. However, if the arbitration domains are determined to be equal, arbitration is performed and transmission of the first and second transactions is serialized. Also contemplated is generating masks corresponding to each of the received transactions. The masks which are generated include an indication of the target domain of the corresponding transaction. When the transaction is conveyed to a port for transmittal, its mask is conveyed as well. Each port includes a domain vector register indicating the domains to which it is connected. By comparing the received mask to the domain vector register, a determination is made as to whether the transaction is to be output on the port or not.

Broadcast arbitration in a multi-domain device

A system may perform interconnect BIST (IBIST) testing on source synchronous links. The system may perform, at normal operating frequency, a source synchronous link test that tests a victim line on the source synchronous link using a transition weave pattern. The transition weave pattern causes interaction between a data transition on the victim line, previous transitions on the victim line, and transitions on the other lines of the link (the 'aggressor' lines). The interaction caused may be: (i) a first crossing pulse on the victim line; (ii) a second crossing pulse of the opposite polarity on each aggressor line concurrent with the first crossing pulse on the victim line; and (iii) a reflection in the opposite direction of the first transition of the first crossing pulse, wherein the reflection results from a previous transition on the victim line.

Source synchronous link integrity validation

A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal. The method and apparatus may include a source synchronous receiver that is hot-swappable.

Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection

A system and apparatus for time multiplexing of multi-domain transactions is provided. A computer system may include multiple domains of clients where the domains share common physical links. The bandwidth on a physical link may be divided between the domains that use that link such that a domain may only convey and receive transactions specific to that domain during the time period allocated to it on that physical link. A counter may be used to partition the bandwidth of a physical link between the domains that use that physical link.

System and method for time multiplexing of multi-domain transactions

In a computer system having a first repeater and a second repeater, the first repeater coupled to the second repeater by a bus, the first repeater operable to transmit a transaction and a control signal to the second repeater, a method, performed by the second repeater, of generating an error comprising: predicting, in a first cycle, that a transaction should be transmitted from the first repeater to the second repeater; determining if a control signal was received within a predetermined number of cycles of the first cycle; and if the control signal is not received within the predetermined number of cycles of the first cycle, then generating an error.

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Sunnyvale, CA, United States of America

Brian L Smith