Intel Corporation

Brian L Dipert

Kurt B Robinson

David M Brown

Russell D Eslick

Lily C Pao

Duane R Mills

Richard D Pashley

Sachidanandan Sambandan

Bruce McCormick

Markus A Levy

Lawrence M Leszczynski

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

Synchronous interface for a nonvolatile memory

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

Asynchronous interface for a nonvolatile memory

A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.

Flash memory including a mode register for indicating synchronous or

An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.

Method and apparatus for performing burst read operations in an

In a computer system having a central processing unit (CPU) coupled to a memory, a method is described for identifying whether the memory is a first type of memory or a second type of memory. A programming voltage is decoupled from a control circuit of the memory such that the control circuit is disabled from accessing a memory array of the memory during a write operation of the memory. The memory is then accessed from the CPU through the write operation for a device identification from the memory. The first type of memory includes the device identification and the second type of memory does not include the device identification. Data integrity of the memory is maintained during the write operation because the memory array of the memory is not accessed during the operation. The memory is then identified as the first type of memory if the CPU receives the device identification from the memory. The memory is identified as the second type of memory if the CPU does not receive the device identification from the memory.

Computer system with a memory identification scheme

A flash memory card is described. One flash memory card has circuitry for providing a ready output signal that indicates a first in time transition from a busy mode to a ready mode by either a first flash memory or a second flash memory of the flash memory card. One flash memory card has a power control register that is used to place certain flash memories in a power down mode. One flash memory card retains information in a power control register from a time prior to the entering of a global power down mode to a time after exiting of the global power down mode. One flash memory card has jumpers for indicating how many flash memories are present on the flash memory card.

Flash memory card with power control register and jumpers

A flash memory card is described. One flash memory card has addressable circuitry for selectively causing first, second, and third flash memories to operate in an active mode concurrently.

Flash memory card with all zones chip enable circuitry

A flash memory card is described which has a plurality of flash memories, each having a ready/busy output for indicating whether its respective one of the plurality of flash memories is busy or ready. A register circuit is provided for storing a plurality of mask data. A mode circuit is provided for choosing one of a first mode and a second mode, wherein a first mode signal is produced if the first mode is chosen and a second mode signal is produced if the second mode is chosen. A logic circuit is provided for performing logical operations with respect to the ready/busy output for each of the plurality of flash memories and the mask data in accordance with whether the first mode signal or the second mode signal is produced. If the first mode is chosen, the logic circuit produces a ready signal output for the flash memory card only if the ready/busy output of all the plurality of flash memories is ready. If the second mode is chosen, the logic circuit produces a ready signal output for the flash memory card each time any flash memory goes from being busy to being ready.

Flash memory card including plural flash memories and circuitry for

A flash memory card is described which includes a first flash memory and a second flash memory. The first flash memory includes an unmasked first output that enters a first state if the first flash memory is ready and a second state if the first flash memory is busy. The second flash memory includes an unmasked second output that enters the first state if the second flash memory is ready and the second state if the second flash memory is busy. The flash memory card also includes a circuit for selectively providing one of (1) a masked first output (2) the unmasked first output, (3) a masked second output, and (4) the unmasked second output. A latch provides a first ready output signal for the flash memory card. The first ready output signal indicates a first transition from the second state to the first state by one of the unmasked first output of the first flash memory and the unmasked second output of the second flash memory. A circuit is also provided for clearing the first ready output signal from the latch.

Flash memory card including circuitry for selectively providing masked

A flash memory card is described which has a ready/busy mask register. First and second flash memories of the flash memory card have respective first and second outputs indicating ready or busy status for the first and second memories. The ready/busy mask register contains mask data. Logic circuitry performs (1) a first logical operation between a first output and a first mask datum to produce a first masked output, (2) a second logical operation between a second output and a second mask datum to produce a second masked output, and (3) a third logical operation between the first masked output and the second masked output to produce a flash memory card ready/busy output. The flash memory card has circuitry for providing a ready output signal that indicates a first (in time) transition from a busy mode to a ready mode by either the first flash memory or the second flash memory of the flash memory card.

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Sacramento, CA, United States of America

Brian L Dipert