Texas Instruments Corporation

Micron Technology Incorporated

Brian L Brown

Christopher B Cooper

David R Brown

Troy A Manning

Charles H Dennison

Stephen L Casper

Shubneesh Batra

Brian M Shirley

Chris G Martin

Roger D Norwood

Ming-Bo Liu

Ronald J Syzdek

Jackson Leung

Pow Cheah Chang

Thanh K Mai

Daniel B Penney

Thanh Kim Mai

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Overflow detection and correction in state machine engines

A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.

METHOD OF STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATION OF DYNAMIC RANDOM ACCESS MEMORY IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT

A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path ( ) receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit ( ). The gate control circuit ( ) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver ( ) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit ( ), the open drain output driver ( ) drives a data output (DQ) to a first, second or intermediate logic level.

Current controlled multi-state parallel test for semiconductor device

A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

METHOD FOR STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD FOR STORING A TEMPERATURE THRESHOLD IN A DYNAMIC RANDOM ACCESS MEMORY, METHOD OF MODIFYING DYNAMIC RANDOM ACCESS MEMORY OPERATION IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT

A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a two-bit register ( ) and output in a sequential fashion to an open drain output driver ( ). In this manner, test result data values are provided by driving an output (DQ) in a rapid sequential fashion, rather than placing the output at one of three states (such as logic high state, a logic low state, or a high impedance state).

Two pass multi-state parallel test for semiconductor device

A DRAM is disclosed that is capable of performing a rapid write-followed-by-read operation. In a preferred embodiment , the DRAM includes a plurality of memory banks ( ), a global write bus ( ), and a global read bus ( ). The global write and read buses ( and ) are coupled to each memory bank ( ) by an associated local read/write circuit ( ). In an initial write operation to a first memory bank ( ), input data on the global write bus ( ) are latched in a first local read/write circuit ( ) associated with the first memory bank ( ). In a subsequent read operation to a second memory bank ( ), as data are output from the second memory bank ( ) onto the global read bus ( ) via a second local read/write circuit ( ), the first local/read write circuit ( ) is simultaneously writing the latched input data into the first memory bank ( ).

Stored write scheme for high speed/wide bandwidth memory devices

A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.

Method and apparatus for efficiently testing RAMBUS memory devices

Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit

A semiconductor memory (,) device having a redundancy test scheme is disclosed. A memory cell array (,) includes a normal section (,) and a redundant section (,and,) of memory cells. In a normal mode of operation, the redundant section is selected if an applied address (ADD) corresponds to a defective bit in the normal section. In a redundant test mode of operation, the redundant section is selected based on a redundant test address (DFTRA, DFTCA). If the redundant test address is in the normal select logic level, a normal decode section (,and,) is selected. The redundant test address and a redundant test activation signal are applied to a redundant decoder (,). If the redundant test address is in a redundant select logic level and the redundant test activation signal is active, the redundant decoder is selectable based on the applied address value.

Redundancy test method for a semiconductor memory

Method and apparatus for efficiently testing rambus memory devices

A semiconductor memory emphasizing manipulated clocking and buffering to increase operating speeds.

Growing community of inventors

Allen, TX, United States of America

Brian L Brown