Analog Devices International Unlimited Company

Linear Technology Corporation

Intrinsix Corporation

Analog Devices,inc.

Brian Kirk Jadus

Steven J Tanghe

Kenneth G Richardson

Eugene Michael Petilli

Deepak Gunasekaran

Michael Collins

Ciaran J Brennan

Eric C Gaalaas

Clyde Washburn

Bikiran Goswami

Mucahit Kozak

John Alvermann

Keith W Bennett

Jason J Ziomek

Dongwan Ha

Art Zirger

A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.

Method to reduce the common-mode EMI of a full bridge converter using sampling common-mode feedback

Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Coding schemes for communicating multiple logic states through a digital isolator

An apparatus and methods to operate the same to provide fast fault-detection on power semiconductor devices such as power transistors are disclosed. In some embodiment, a desaturation based fault-detection circuit for a power transistor is provided. The fault-detection circuit has an adaptable blanking time and a disconnect switch in the blanking mechanism that allow for quick enabling of fault-detection mechanisms to achieve fast fault detection times on power semiconductor devices.

Apparatus and method to achieve fast-fault detection on power semiconductor devices

A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Gate driver with pulsed gate slew control

An electronic circuit comprises a power switch and a fault detection circuit. The power switch circuit includes a power switch transistor. The fault detection circuit includes a comparator circuit configured to monitor a voltage across the power switch transistor and compare the voltage to a varying threshold voltage that decreases with time, and produce an indication of a circuit fault when the voltage of the power switch transistor is greater than the time varying threshold voltage.

Overcurrent protection detector with dynamic threshold for power conversion switch

An electronic circuit comprises a power switch circuit and a fault detection circuit. The power switch circuit includes a transistor. The fault detection circuit includes a first comparator circuit configured to compare a monitored voltage of the transistor to a detection threshold voltage and produce an indication of a circuit fault according to the comparing, and a delay circuit configured to delay the comparing by the first comparator circuit according to slew rate of the monitored voltage.

Adaptive blanking of over current fault detection circuits in power conversion gate drivers

A device is configured to control a transition timing of a switching DC/DC converter for providing power to a load device. The load device has a first operational phase that is sensitive to external noise and a second operational phase that is immune to the external noise. The device includes an input terminal coupled to an external device to receive a start signal of the first operational phase for the load device. The device also includes control circuitry configured to, responsive to the start signal, control a transition frequency of the DC/DC converter to avoid transitioning an output of the switching DC/DC converter during the first operational phase.

Transition timing control for switching DC/DC converter

This disclosure describes a circuit implementation providing the functions necessary to implement an isolated IC bidirectional port. The technique implements a current source as a pull up device on at least one side of the isolation system. The circuit manages and communicates bidirectional data across an isolation barrier. A method of communicating bidirectional signals and an IC acknowledge (ACK) or clock stretching through an isolation channel is disclosed.

[object Object]

An apparatus and method for a Universal Serial Bus (USB) isolating device. An USB isolating device includes a downstream facing circuit and a upstream facing circuit. The downstream facing circuit is coupled to a peripheral device via a first pair of signals and is configured for detecting a speed at which the peripheral device is operating based on a first voltage configuration on the first pair of signals. The upstream facing circuit is coupled to the downstream facing circuit and a host/hub via a second pair of signals and is configured for communicating with the downstream facing circuit on the speed of the peripheral device and adaptively creating a second voltage configuration on the second pair of signals to facilitate the host/hub to adapt to the speed of the peripheral device.

Method and system for detecting and asserting bus speed condition in a USB isolating device

Method and system for serially sending data signals captured from multiple sources through a single unidirectional isolation component. Data signals from respective multiple sources are captured in parallel. Such captured data signals are stored in respective storages. The stored data signals are transferred, in serial, from the storages to a single unidirectional isolation component. Multiple concurrent processes for parallel data signal capture and serial data signal transfer via a single unidirectional isolation component are implemented so that the sampling effect on a first of the multiple processes is minimized.

Method and system for communicating multiple data signals over a single unidirectional isolation component

Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a sigma-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Hybrid heterodyne transmitters and receivers

A sigma delta modulator (SDM) data converter system is provided. The SDM data converter system comprises a signal path, a feedback signal path, and a multi-bit quantizer disposed in a feedforward path. The signal path receives an input signal to be processed. The feedback signal path provides a feedback signal that is subtracted from the input signal. The multi-bit quantizer is disposed in the feedforward path so as to receive the input signal after the feedback signal has been subtracted from it. Te multi-bit quantizer uses feedforward dynamic element matching (DEM) to spectrally shape mismatch errors in the SDM data conversion system and produce an output signal, wherein the output signal of the multi-bit quantizer is used for at least a portion of the feedback signal.

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Williston, VT, United States of America

Brian Kirk Jadus