International Business Machines Corporation

Kabushiki Kaisha Toshiba

Globalfoundries Inc.

Mediatek Corporation

Sony Computer Entertainment Inc.

Brian King Flachs

Brad William Michael

Mark Richard Nutter

Charles Ray Johns

Kathryn Mary O'Brien

Tong Chen

Sang Hoo Dhong

Harm Peter Hofstee

Tao Zhang

John K P O'Brien

John Samuel Liberty

Alexandre E Eichenberger

Gilles Gervais

Osamu Takahashi

Michael Norman Day

Ulrich Weigand

Makoto Aikawa

Tetsuji Tamura

Matthew Edward King

Jeffrey A Stuecheli

Michael Steven Siegel

Bartholomew Blaner

Joel Abraham Silberman

Kevin John Nowka

Seiji Maeda

Jonathan James DeMent

John Kevin Patrick O'Brien

David W Cummings

Iwao Takiguchi

Ayal Zaks

H Peter Hofstee

Adam P Burns

Steven Osman

Barry L Minor

Hugh Thomas Mair

Mack Wayne Riley

Nicolas Maeding

Huajun Wen

Robert Michael Dinkjian

Bill N On

Yaping Zhou

Louis Bernard Bushard

Hiroo Hayashi

Shigeaki Iwasa

Douglas Hooker Bradley

Steven Joseph Smolski

Paul Marlan Harvey

Michael Timothy Saunders

Stephen Douglas Posluszny

Yoichi Nishino

Michael Alan Kutner

Ira Rosen

Jaehong Park

Michael Y Lee

Heinz Baier

Christopher R Conley

Paula Kristine Coulman

Dorit Nuzman

Michael Brian White

Naxin Jason Wang

Revital Erez

Hsin-Chen Chen

A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.

Dynamic power meter with improved accuracy and single cycle resolution

Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

Arranging binary code based on call graph partitioning

Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Parallel execution unit that extracts data parallelism at runtime

Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Selection of post-request action based on combined response and input from the request source

In response to receiving a selection to override an existing memory allocation of one or more regions of an external memory device within a memory register for a particular bridge from among multiple bridges within an integrated circuit, wherein the multiple bridges connect to a shared physical memory channel to the external memory device, a remap controller of the particular bridge reads, from a super rank register, one or more super rank values specifying one or more relocation regions of the external memory device connected to an interface of the integrated circuit. The remap controller remaps the memory register for the particular bridge with the one or more super rank values specified in the super rank register to relocate memory accesses by the bridge to the one or more relocation regions of the external memory device.

Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory

A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Multithreaded programmable direct memory access engine

A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effective address matches the requested effective address, the cache manager identifies a corresponding cache location and retrieves the data from the identified cache location. However, when the most recently used effective address fails to match the requested effective address, the cache manager determines whether the requested effective address matches a subsequent effective address stored in the mapped tag vector. When the cache manager determines a match to a subsequent effective address, the cache manager identifies a different cache location corresponding to the subsequent effective address and retrieves the data from the different cache location.

Efficient multi-level software cache using SIMD vector permute functionality

Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

Dynamically rewriting branch instructions in response to cache line eviction

A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies 'if-then-else' statements that offer opportunity for conditional branch conversion. The SIMD IHS employs a processor or processors to execute the executable program. During execution, the processor generates and updates SIMD lane mask information to track and manage the conditional branch loops of the executing program. The processor saves branch addresses and employs SIMD lane masks to identify conditional branch loops with different branch conditions than previous conditional branch loops. The processor may reduce SIMD IHS processing time during processing of compiled code of the original 'if-then-else' statements. The processor continues processing next statements inline after all SIMD lanes are complete, while providing speculative and parallel processing capability for multiple data operations of the executable program.

Management of conditional branches within a data parallel system

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Georgetown, TX, United States of America

Brian King Flachs