Nvidia Corporation

Brian Kelleher

Franck Diard

Anthony Michael Tamasi

Philip Browning Johnson

Mark Douglas Hummel

Emmett Michael Kilgariff

Samuel Hammond Duncan

Glenn A Dearth

Denis J Foley

John R Feehrer

Ludger Mimberg

Vyas Venkataraman

Ram Gummadi

Jonah Matthew Alben

Sean Jeffrey Treichler

David G Reed

John M Danskin

Dennis K Ma

Kevin J Kranzusch

Wayne Yamamoto

Senthil S Velmurugan

Carl W Davies

John Lam

Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Techniques for an efficient fabric attached memory

Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

Techniques for balancing accesses to memory having different memory types

Embodiments of the present technology are directed toward techniques for enabling different memory partitions to have different memory depths.

Techniques for different memory depths on different partitions

An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Design, layout, and manufacturing techniques for multivariant integrated circuits

Embodiments of the claimed subject matter are directed to systems and a method that allows the aggregation of multiple interfaces of a single data communication bus to provide greater bandwidth for communication between a peripheral device and system memory within a computing system. In one embodiment, a system is provided wherein the unoccupied interfaces of the data communication bus is aggregated with an occupied interface coupled to a peripheral device to increase the bandwidth of data transfer requests between the peripheral device and the system memory.

Aggregating unoccupied PCI-e links to provide greater bandwidth

A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.

Method and system for implementing compression across a graphics bus interconnect

An electronic device is assigned to a virtual bin by setting an operating voltage of the electronic device to a first voltage, determining an operating frequency and an operating power consumption level for the electronic device, determining an operating frequency differential equal to the absolute value of difference between the operating frequency and a minimum operating frequency of the physical bin, determining a power consumption level differential equal to the absolute value of difference between the operating power consumption level and a maximum operating power consumption level of the physical bin, and assigning a virtual bin identifier to the electronic device to identify the operating voltage of the electronic device if the operating frequency is greater than or equal to the minimum operating frequency of the physical bin and the operating power consumption level is less than or equal to the maximum power consumption level of the physical bin.

Virtual binning

Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors.

Distributed antialiasing in a multiprocessor graphics system

The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g.,D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.

Processor performance adjustment system and method

A system and method for optimizing power usage and performance during data processing. A multi-processor graphics processing system includes a low power graphics processor and a high performance graphics processor. When a low power condition exists only the low power graphics processor is used to process graphics data and the high performance graphics processor is turned off. When turned off, the high performance graphics processor does not consume either static or dynamic power. When the low power condition does not exist, the high performance graphics processor is turned on and the low power graphics processor and the high performance graphics processor are used to process the graphics data.

Optimizing power and performance for multi-processor graphics processing

One embodiment of a reconfigurable graphics processing system includes a first MXM edge connector and a second MXM edge connector affixed to an interposer board and a first MXM board and a second MXM board coupled to the interposer board via the first and second MXM edge connectors, respectively. Each MXM board includes a GPU and other elements necessary to process graphics data. The system couples to the motherboard of a computing device through an interface connector on the interposer board. One advantage of such a system is that it may be configured to deliver more performance than a standard desktop graphics board, while occupying substantially the same volume, through the use of multiple, small form factor MXM boards.

Reconfigurable graphics processing system

A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs pixel processing in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be utilized as part of a master/slave pair.

Apparatus, system, and method for joint processing in graphics processing units

A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs a graphics processing operation in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be packaged as part of a master/slave pair.

Growing community of inventors

Palo Alto, CA, United States of America

Brian Kelleher