Motorola Corporation

Brian Keith Reynolds

Michael D Snyder

Michael Julio Garcia

David W Todd

Christopher Bryant

A bus protocol for a split bus (,) where each device (,) coupled to the bus has an age-based queue (,) of pending transactions. Queues are updated as transactions are executed. A central arbiter (,) has a copy of each device's queue (,). A priority transaction is determined from among all the queues in the arbiter. A data transaction index (DTI) is broadcast during the data tenure to all devices indicating the position in the queue of the next transaction. The index allows out-of-order data transfers without the provision of a static tag during the address tenure. Queues maintain a history of pending transactions. In one embodiment, each device receives a separate data bus grant (DBG), allowing a single provision of the index to both a source and a sink device.

Method and apparatus for transferring data on a split bus in a data processing system

A method of transferring data between a slave device (20) in communication with a processor interface bus (34) where the processor interface bus is in communication with a master device (12) including receiving an address from the processor interface bus (34) where the address was provided by the master device (block 302). A first signal is asserted (blocks 318 and 324) on the processor interface bus (34) to indicate that the slave device (20) is servicing a data transfer transaction. A second signal is asserted (block 320) on the processor interface bus (34) to indicate whether data to be transferred using the processor interface bus (34) is to be stored in main memory (36) by a main memory controller (32) in communication with the processor interface bus (34). The data is transferred (block 326) between the slave device (20) and the processor interface bus (34).

Method and apparatus for transferring data over a processor interface bus

An interbus buffer (18) coordinates data transfers between two different sized buses. The first bus (processor bus) allows data to be ordered according to either a big endian protocol or a 'munged' little endian mode. The second bus (local bus) allows data to be ordered according to either a big endian protocol or a true little endian mode but does not define a transaction size. The disclosed interbus buffer coordinates interbus data transfers in spite of the variety of different transaction sizes and operating modes.

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Round Rock, TX, United States of America

Brian Keith Reynolds