The Mathworks, Inc.

Brian Keith Ogilvie

David H Koh

Pieter Johannes Mosterman

Donald Paul Orofino, Ii

Charles J Devane

Alireza Pakyari

Kiran K Kintali

Zhihong Zhao

Jing Ma

Zhongxin Li

Jihad E Ibrahim

Shi Chao Zhang

John Edward Ciolfi

Jared D MacDonald

Darel Allen Linebarger

Rajiv Ghosh-Roy

Katalin Maria Popovici

Witold Robert Jachimczyk

John Zhao

Marc David Erickson

Bharath Venkataraman

Bharath Venkateraman

Mukesh K Chugh

Michael Neil Hanson

Adam C Leon

Paul Costa

Garrey William Rice

A device may receive information associated with an input image that includes a first quantity of rows. The device may store pixel values, for a second quantity of rows, based on the information associated with the input image. The second quantity of rows may be different than the first quantity of rows. The device may generate an output image, that includes a projective transformation of the input image, based on the stored pixel values. The device may provide information associated with the output image.

Memory efficient on-chip buffering for projective transformation

A system and method automatically generates graphical model from an object-oriented, textual program, and verifies the performance of the graphical model to the textual program. The textual program may include a plurality of system objects having properties. The objects may be mapped to graphical model blocks that have parameters. The properties of the system objects may be mapped to the parameters of the graphical model blocks.

System and method for automatically generating a graphical model from a text-based program

A mechanism for converting a graphical model of a system into an intermediate representation (IR) of a model is discussed. The mechanism alters the IR, and uses the altered IR to create a new or updated graphical model of the system that may be viewed and simulated by a user. Once the user is satisfied with the alterations to the IR, the IR or the graphical model may be used to generate code in a target language to enable the building of the physical system being designed. The use of the altered IR to generate a new or updated graphical model allows a more efficient and customizable design and simulation process than is typically found by simulating code that has been converted to target languages. The generation of the graphical model based on the altered IR allows a user to visually inspect the changes to the system, and the simulation of the graphical model based on the altered IR allows corrective action to be taken to account for any changes that occurred during the transformation of the model.

System and method for transforming graphical models

A device receives information specifying a functional model that includes a set of variables and a set of computations, and receives debugging information associated with the functional model. The device generates computer code based on the set of computations associated with the functional model, the set of variables associated with the functional model, and the received debugging information. The device executes the generated computer code based on the debugging information.

Unified hardware and software debugging

The present invention provides a method and system for automatic verification of automatically generated standalone code intended for execution on a target computing platform against its original design simulated in a simulation environment. The present invention also applies to execution comparisons between two implementations, such as two simulations, one simulation and one standalone code implementation, or two standalone code implementations. Block diagrams can be used to create a comparison model that compares two implementations. The comparison of different implementations can be performed at a block level, a subsystem level, a model level, or multi-model level. The present invention allows automatic comparison once a user supplies the intermediate outputs and/or signals that the user wants to compare and monitor. Reports can be generated to show the statistics of the comparison results.

Automatic comparison and performance analysis between different implementations

A minimum resource FFT design may calculate the FFT for an input data series using minimal logic resources to implement the FFT. In one implementation, the FFT design may include a butterfly component for performing one or more complex addition and multiplication operations and outputting a plurality of results; a first memory coupled to the butterfly component, the first memory including a number of memory banks equal in number to the number of the plurality of the results; a second memory coupled to the butterfly component, the second memory including a number of memory banks equal in number to a number of the plurality of the results; and a control component to control reading and writing from the first and second memories and the butterfly component using a ping-pong access technique that reads and writes intermediate values to the first and second memories to implement the FFT.

Minimum resource fast fourier transform

A system and method automatically generates an object-oriented, textual program from a graphical model, and verifies the performance of the textual program as compared to the graphical model. The graphical model may have a plurality of interconnected blocks, and each block may have a plurality of parameters. One or more of the blocks are mapped to a system object, and the block's parameters are mapped to properties of the system object. An object-oriented, executable textual string is generated automatically for the block. The generated string includes at least one command to: instantiate a system object having functionality that matches the block; set one or more properties of the system object based on the block's parameters; and run the instantiated object.

Verification harness for automatically generating a text-based representation of a graphical model

A device determines a portion of data generated by a technical computing environment (TCE) program, where the portion of the data is determined based on an initial availability of a resource of a server device. The device provides the portion of the data to the server device for execution, and receives, from the server device, results associated with execution of the portion of the data. The device calculates an availability of the resource based on the results associated with execution of the portion of the data, and provides, to the server device for execution, additional data generated by the TCE program, where the additional data is determined based on the availability of the resource of the server device. The device receives, from the server device, results associated with execution of the additional data, where the receiving is performed by the device.

Dynamic arbitrary data simulation using fixed resources

An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Algorithm and architecture for multi-argument associative operations that minimizes the number of components using a latency of the components

Exemplary embodiments allow configurable execution of operations associated with a state enabled system in a graphical modeling or graphical programming environment. In an embodiment, a state enabled system may be identified in a graphical model, or a graphical program, or both. The state enabled system may be associated with a first operation and a second operation, and may include instructions to execute the first and second operations. The state enabled system may be configured to always execute the first operation regardless of an enabling condition. The state enabled system may also be configured to prevent an execution of the second operation unless the enabling condition is satisfied.

Configurable enablement of operations associated with state enabled systems in a graphical environment

A modeling system includes a graphical programming environment that receives a first graphical model from a user. The system may also receive a configuration control set for the first graphical model. A code generation engine converts the first graphical model into an intermediate representation (IR). A second graphical model is created from the IR and the configuration control set. The second graphical model is displayed to the user, and may be subject to one or more modifications. Code in a target language may be generated from the second graphical model.

An automatic code generation application is used to automatically generate code and build programs from a textual model or graphical model for implementation on the computational platform based on the design. One or more model elements may be capable of frame-based data processing. Various options and optimizations are used to generate Hardware Description Language (HDL) code for the frame-based model elements.

Growing community of inventors

Holliston, MA, United States of America

Brian Keith Ogilvie