National Instruments Corporation

Brian Keith Odom

Hugo A Andrade

Cary Paul Butler

Jeffrey L Kodosky

Sundeep Chandhoke

Joseph E Peck

James J Truchard

Newton G Petersen

Kevin L Schultz

Craig M Conway

Rodney W Cummings

Glen O Sescila, Iii

Robert W Canik

Matthew E Novacek

Garritt W Foote

Duncan G Hudson, Iii

Changzhe Gao

Andrew C Mihal

Gregory O Morrow

Perry C Steger

Bob Mitchell

James C Nagle

Rishi H Gosalia

Rafael Castro

David L Potter

Brian C MacCleery

William C Nowlin, Jr

J Marcus Monroe

Alexandre M Barp

Rafael Castro Scorsi

Neil S Feiereisel

Kyle R Bryson

Jeffrey J Kellam

M Dean Brockhausen, Jr

Pratik Mukundray Mehta

Dustyn K Blasig

Andrew C Thomson

Christopher Frederick Graf

Arthur M Ryan

Kunal H Patel

William R Pitts

Jeronimo Mota

Timothy A Stelzer

Jeremy Willden

Michael G Jablin

C Paul Butler

Nigel D Waites

Ryan P Verret

Joseph H DiGiovanni

Systems and methods for interoperating between real time networks. Systems may include a plurality of ports and switch circuitry coupled to the plurality of ports. At least one port may be coupled to a first real time network carrying first traffic. One or more other ports may be coupled to a second real time network carrying second traffic. Switch circuitry may route packets between the first real time network and the one or more second real time networks based on a mapping. Routing information may be inserted in packets routed from the one or more second real time networks to the first real time network and routing information may be removed from the packets routed from the first real time network to the one or more second real time networks. Packets may be routed based on the mapping to distinct queues for the first and second traffic.

System and method for interoperability between multiple networks

Systems and methods for interoperating between networks. A first network may be configured to operate according to a first real time network protocol and each of one or more second networks may be configured to operate according to respective second real time traffic protocols. A mapping may specify data routing between a plurality of ports and the routing may maintain real time behavior between the first network and the one or more second networks. Additionally, routing information may be inserted in packets routed from the one or more second networks to the first network and removed from packets routed from the first network to the one or more second networks. The packets may be routed, based on the mapping, to distinct queues for the first network and the one or more second networks for processing by an application executing on at least one device.

Systems and methods for network interoperability

Systems and methods for scheduling data egress from a network switch. Systems may include switch circuitry, a plurality of ports, and a plurality of queues. Each port may be associated with a respective set of routing information for network packets and each port may be configured with a respective set of egress periods. Each network packet may have respective routing information and a type that specifies a respective egress period. Each queue may be associated with a respective network packet type and a port of the plurality of ports.

Switch for scheduled data egress

System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Graphical development and deployment of parallel floating-point math functionality on a system with heterogeneous hardware components

System and method for extending programmable device functionality while preserving functionality of the device driver and driver IP. User input may be received specifying functionality of custom IP for a programmable measurement device with standard driver IP. The custom IP may be generated accordingly, and may be deployable to the programmable measurement device. During operation the custom IP may communicate directly with the standard driver IP and may provide custom functionality of the programmable measurement device while preserving functionality of the standard driver IP on the programmable measurement device and the standard device driver.

Extending programmable measurement device functionality

Systems and methods for mapping a time-based data acquisition (DAQ) to an isochronous data transfer channel of a network. A buffer associated with the isochronous data transfer channel of the network may be configured. A clock and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the time-based DAQ, transfer data to the local buffer, initiate transfer of the data between the local buffer and the buffer at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the buffer. The buffer may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the time-based DAQ to the isochronous data transfer channel of the network.

Lossless time based data acquisition and control in a distributed system

Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network.

Global optimization and verification of cyber-physical systems using graphical floating point math functionality on a heterogeneous hardware system (HHS). A program includes floating point implementations of a control program (CP), model of a physical system (MPS), objective function, requirements verification program (RVP), and/or global optimizer. A simulation simulates HHS implementation of the program using co-simulation with a trusted model, including simulating behavior and timing of distributed execution of the program on the HHS, and may verify the HHS implementation using the RVP. The HHS is configured to execute the CP and MPS concurrently in a distributed manner. After deploying the program to the HHS, the HHS is configured to globally optimize (improve) the CP and MPS executing concurrently on the HHS via the global optimizer. The optimized MPS may be usable to construct the physical system. The optimized CP may be executable on the HHS to control the physical system.

Global optimization and verification of cyber-physical systems using floating point math functionality on a system with heterogeneous hardware components

Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port.

Switch for scheduled time-sensitive data egress

Time-sensitive switch for scheduled data egress

Systems and methods for interoperating between a time-sensitive (TS) network and a non-time-sensitive (NTS) network. The system may include a TS network switch and a TS network interface controller (NIC). Each may have a functional unit. A first port of the TS switch may be coupled to an NTS node of the NTS network and its functional unit may be configured to manage insertion and removal of tags associating packets received from the NTS network with the NTS network. The tagged packets may be forwarded on to the TS NIC via a second port. The functional unit of the TS NIC may be configured to queue tagged packets received from the TS network switch and queue and tag packets destined for the NTS network via the TS network switch.

System and method for debugging a graphical program deployed to hardware. The graphical program may be received. The graphical program may include a plurality of nodes and connections between the nodes which visually represents functionality of the graphical program. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be deployed to the programmable hardware element and the programmable hardware element may be executed. The graphical program may be displayed on a display of a host computer system that is coupled to the programmable hardware element. Debugging information may be received from the programmable hardware element during the executing. The debugging information from the programmable hardware element may be displayed in the graphical program displayed on the display. The displayed debugging information may be used to debug the hardware implementation of the graphical program.

Debugging a graphical program deployed on a programmable hardware element

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Georgetown, TX, United States of America

Brian Keith Odom