Texas Instruments Corporation

Applied Materials, Inc.

Brian Keith Kirkpatrick

James Joseph Chambers

Amitabh Jain

Freidoon Mehrad

Rajesh B Khamankar

Clinton L Montgomery

Hiroaki Niimi

Mark H Somervell

Douglas Ticknor Grider

Husam N Alshareef

Malcolm John Bevan

Seung-Chul Song

April Gurba

Chet Vernon Lenox

Brian J Brown

Shaofeng Yu

Deborah J Riley

Ekaterina A Mikhaylichenko

David Gerald Farber

Andrew McKerrow

Jon Holt

Edmund G Russell

Ping Jiang

Dirk N Anderson

Jinhan Choi

Joe G Tran

Steven Lee Prins

Kenneth Joseph Newton

Zhihao Chen

Brian M Trentman

Byron Joseph Palla

Jeff White

Randall W Pak

Jason D Mehigan

Michael Morrison

Andrew Marshall

Mahalingam Nandakumar

Jiong-Ping Lu

Abbas Ali

Stephen A Keller

Gabriel George Barna

Tom Lii

John Howard MacPeak

Donald S Miles

Brian Edward Hornung

Clint Montgomery

Rajesh Tiwari

Eddie Hearl Breashears

Alfred J Griffin, Jr

Christopher Scott Whitesell

Mercer Brugler

Ralf B Willecke

Chad J Kaneshige

Melissa M Hewson

Glenn J Tessmer

Thomas M Parrill

Der'E Jan

Kenneth Palomino

Corbett Zabierek

Victor Watt

Beth Walden

Balasubramanian's Pranatharthiharan

Lu Jiong-Ping

Andrew J Mckerrow

Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a metal deposition chamber coupled with the transfer chamber.

Integratead wet clean for bevel treatments

A method for removing particulates from a plurality of substrates includes opening a first access port in a top of a first container holding a cleaning fluid bath, inserting a first substrate through the first access port to a first support, closing the first access port, opening a second access port in the top of the first container, inserting a second substrate through the second access port to a second support, closing the second access port, opening the first access port, removing the first substrate through the first access port and delivering the first substrate into a rinsing station, closing the first access port, opening the second access port, removing the second substrate through the second access port and delivering the second substrate into the rinsing station, and closing the second access port.

Cleaning method with in-line SPM processing

Cleaning chambers may include a substrate support having a substrate seating position. The cleaning chambers may include a plurality of fluid nozzles facing the substrate support. Each fluid nozzle of the plurality of fluid nozzles may define a fluid port characterized by a leading edge and a trailing edge. Each fluid nozzle of the plurality of fluid nozzles may be angled relative to the substrate seating position of the substrate support to produce an interior angle of greater than or about 90° at an intersection location across the substrate seating position for a fluid delivered from each fluid nozzle at the leading edge of the fluid port.

Surface cleaning with directed high pressure chemistry

Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Reduced semiconductor wafer bow and warpage

A cleaning system for processing a substrate after polishing includes a sulfuric peroxide mix (SPM) module, at least two cleaning elements, and a plurality of robots. The SPM module includes a sulfuric peroxide mix (SPM) cleaner having a first container to hold a sulfuric peroxide mix liquid and five to twenty first supports to hold five to twenty substrates in the liquid in the first container, and a rinsing station having a second container to hold a rinsing liquid and five to twenty second supports to hold five to twenty substrates in the liquid in the second container. Each of the at least two cleaning elements are configured to process a single substrate at a time. Examples of a cleaning element include a megasonic cleaner, a rotating brush cleaner, a buff pad cleaner, a jet spray cleaner, a chemical spin cleaner, a spin drier, and a marangoni drier.

Cleaning system with in-line SPM processing

A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

Split gate memory cell fabrication and system

A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer thereon including a field dielectric in a portion of the semiconductor surface layer and a pair of matched devices in at least one of a CMOS area, BiCMOS area, bipolar transistor area, and a resistor area. Dopants are ion implanted into the at least one of the CMOS area, the BiCMOS area, the bipolar transistor area, and the resistor area. The substrate is annealed in a processing chamber of a rapid thermal processor (RTP). The annealing comprises an initial temperature stabilization step including first annealing at a lower temperature for a first time of at least 20 seconds, and then a second annealing comprising ramping from the lower temperature to a peak higher temperature that is at least 100&#xb0; C. higher (&#x3e;) than the lower temperature.

Dopant anneal with stabilization step for IC with matched devices

A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

Method for stripping one or more layers from a semiconductor wafer

A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

Integrated circuit having chemically modified spacer surface

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Method of fabricating semiconductors

An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

Inner L-spacer for replacement gate flow

An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

High-k / metal gate CMOS transistors with TiN gates

Growing community of inventors

Allen, TX, United States of America

Brian Keith Kirkpatrick