Lsi Logic Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Ncr Corporation

Symbios Logic Inc.

Symbios, Inc.

Ld Electronics

Brian K Herbert

Jamey L Robbins

William K Petty

John Matthew Adams

Stephen M Johnson

Coralyn S Gauvin

David L Henderson

Michael D Lahey

Richard W Koralek

Luke Saucier

Richard W Hale

A drive through order system having a vehicle detection system that includes at least two sensors, each affixed to an immovable object, a CPU coupled to a computer readable medium containing instructions to process information from the sensors using fuzzy logic and to output an indicator signal reflecting the presence of a vehicle within a volume sensed by the sensors. In some embodiments, a learn mode supports alteration of fuzzy logic processing parameters. In various embodiments, the system is upgradable and sensor types can be changed and/or new sensors added. In some embodiments, fuzzy logic processing information is modified in dependence upon temporal information.

Drive through order system and vehicle detection

A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generate which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.

Method and apparatus for utilizing a data processing system for multi-level data communications providing self-clocking

A precision delay circuit having two delay chains to provide equal delay periods is described. A rising edge of an input pulse signal is supplied to the first delay chain and the falling edge is supplied to the second delay chain. The resultant output signal maintains the pulse width of the input signal and pulse distortion is minimized. In another aspect, a delay circuit for generating a delayed assertion signal that does not maintain the width of the original input signal pulse and which is substantially immune to noise problems is described. An assertion edge of a resultant pulse is timed by the incoming pulse, but the de-assertion edge is timed by the delayed de-assertion edge of the incoming pulse.

Dual path asynchronous delay circuit

A DMA controller including an XOR FIFO buffer and XOR circuitry for computation of parity. The DMA controller resides within a RAID controller and establishes a direct data connection from host memory to subsystem local memory in order allow the CPU to perform other functions. The DMA controller accesses data segments from host memory corresponding to blocks of data within a disk stripe. As the data is transferred from host memory to subsystem local memory, the XOR circuitry simultaneously computes the parity corresponding to the successive data segments. Computing parity substantially simultaneously with the DMA data transfer reduces memory bandwidth utilization on the memory bus of the RAID controller. The parity is stored in the XOR buffer. Once parity is computed for a portion of data segments corresponding to a data stripe, the parity is transferred to local memory for retention. These steps are repeated until the full stripe is read into local memory and a parity value is computed for the entire data stripe. Once the RAID controller is ready to post the data to disk, the data is transferred from local memory to disk. The DMA controller of the present invention may also be advantageously applied when performing partial stripe writes by reducing the memory bandwidth utilization required to compute partial parity values.

DMA controller of a RAID storage controller with integrated XOR parity

The invention concerns loading data into VIDEO RAM in a computer. A processor delivers data to VIDEO RAM by using 'STRING OPs,' which are data-copying operations wherein a field of consecutive data words is copied from one location (such as character memory) to a range of consecutive addresses at another location (such as VIDEO RAM). The invention intercepts the words intended for the consecutive addresses, and distributes them into VIDEO RAM at evenly spaced, non-consecutive addresses. When a graphics controller generates pixels on a display, based on these evenly-spaced addresses, the pixels will automatically occupy a vertical column on the display.

Step addressing in video RAM

A transfer of data between the first clock domain to the second clock domain is synchronized in a situation in which the first clock signal in the first clock domain is generated from a source independent from the second clock signal in the second clock domain. The ratio of one frequency to another is determined along with the phase relationship between the two clock signals during a selected period of time. Then, the phase relationship is predicted for a future period of time. This prediction of the relationship between the two clock signals serves as an input to a control mechanism, which prevents sampling of data and control signals when they are transitioned from one state to another.

Method and apparatus for synchronizing data transfer

A scaling apparatus is disclosed for horizontally and vertically scaling scan line information stored in a video memory prior to providing the scan line information to a computer display. Horizontal scaling apparatus is provided in which a first clock signal is provided for graphics portions of scan lines and a second clock signal is provided for video portions of scan lines. The second clock signal is enabled in a manner such that the second clock signal exhibits a predetermined phase relationship with respect to the first clock signal from scan line to scan line. The frequency of the second clock signal is selected to determine the scaling of the video portion of the scan line. Vertical scaling apparatus is provided in which scan line information corresponding to first and second scan lines is retrieved from a video memory. A digital differential analyzer, external to the central processing unit, then determines respective weights for the first and second scan lines dependent on the amount of vertical scaling desired. The weights for the first and second scan lines are then provided to a weighted adder which adds the first and second scan lines according to these weights.

Image processing apparatus including horizontal and vertical scaling for

A method for transferring data from a first clock domain to a second clock domain. A first clock signal is generated for the first clock domain from a base clock signal. A second clock signal is generated for the second clock domain from the base clock signal. A phase relationship is detected between the first clock signal and the second clock signal. Data is transferred from the first clock domain to the second clock domain using the phase relationship between the first clock signal and the second clock signal.

The clock rate for a device is controlled through the use of integrated circuits which respond to the temperature of the device. Circuitry is added to the integrated circuit device being controlled which changes the clock rate of the device as the device temperature changes. The device clock is thus regulating by the temperature of the device. The way in which the regulation is implemented can be varied, from slowing an internally generated clock rate, or by digitally scaling an external clock input. Synchronous scaling is also provided, such that devices which are connected external to the CPU can still be clocked at the same external rate, but CPU transactions within the CPU may occur at a different rate depending on the CPU's measured temperature. This invention also provides the ability to selectively reduce or stop certain areas of an integrated circuit relative to pending operations or instructions being executed.

Method and apparatus for regulation of power dissipation

The present invention relates to a touch sensitive LCD flat panel display. The display allows a user to provide input into a computer device by simply touching an LCD display screen with a passive device, such as a finger, stylus, or a ball point pen. The invention includes circuitry which continuously compares the charge times of the liquid crystal elements of the display to a reference value and uses the results of the comparison to determine which elements in the display are currently being touched.

Touch sensitive flat panel display

A method and architecture for a graphics controller chip. The graphics controller has a display memory for storing video and graphics data. It also has a logic controller, connected to the memory, for performing logic operations on data stored in the memory. Video and graphics data is made available to the graphics controller at a single access port. The graphics controller also has an address range detector for checking the address of the data provided to the port and for disabling logical operations of the logic controller when the address indicates the presence of video data. The video data is thereafter transferred to the display memory on a priority basis.

Dual-mode graphics controller with preemptive video access

The invention concerns the simultaneous display of video data and text data on a computer display. The invention stores both types of data in display memory. Transition codes mark the separation between the two types. The invention converts each type of data into signals which a CRT display can understand. The invention changes the type of conversion, as appropriate, when transition codes are reached.

Mixed format video ram

An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer. The display data in the pixel output buffer is subsequently interpreted into colors and intensities, and displayed on the CRT screen using known techniques. The vertical and horizontal locations of the cursor are synchronously incremented on a pixel by pixel basis during the scan of a frame buffer line. At the appropriate location, cursor data is multiplexed and/or logically combined with the bit stream of frame buffer data to overlay the cursor characteristics upon the video display data. The cursor data buffer can thereby be relatively small yet overlay a relatively large cursor with minimal manipulation by the computer controlling the video display.

Bit mapped color cursor

A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.

Random access memory device with integral logic capability

An interface controller, situated between a graphics controller and a memory array in a color video display system operable in a read-modify-write mode, configured to detect a select transparency color in whole or in part and to respond by selectively changing the color binary data for the corresponding pixel in a frame buffer. In another aspect, the invention includes drawing modes impelmented by logically combining pixel color binary data in accordance with a defined truth table so as to allow the pixel color data representing a new image to interact in a defined manner based upon color with the data in a previously defined image. As implemented, the binary data in the frame buffer is acted upon in a read-modify-write sequence whereby the various logic operations analyze the source (foreground) pixel data, the destination (background) pixel data, in the context of control signals, to define the pixel color data written into the frame buffer as the color representation for that pixel position.

Growing community of inventors

Colorado Springs, CO, United States of America

Brian K Herbert