Lsi Corporation

Palmchip Corporation

Brian K Gutcher

Kripa Venkatachalam

Lyle E Adams

Michael Ou

S Jauher A Zaidi

Jef Munsil

Stephen Chappell

Savitha Gandikota

Jon Udell

Methods and circuits comprising a reliability measurement unit (RMU) for generating log-likelihood ratio (LLR) values corresponding to 1T for use in a soft output Viterbi algorithm ('SOVA') decoder. The RMU operates with an nT clock signal. 1T signals generated by an add, compare, select circuit (ACS) of the SOVA generates 1T decision data and a path equivalency detector generates 1T path equivalency information for 1T SOVA decoding and applies the 1T data to the RMU operating with an nT clock frequency (1/n'th that of the 1T clock signal). The nT RMU receives a plurality of 1T inputs on each nT clock signal pulse and generates 1T LLR information for use by the SOVA decoder. Other components of the SOVA may also operate using the nT clock signal pulse or may operate using a 1T clock signal.

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Methods, apparatus, and systems for generating bit-wise path equivalency information corresponding to 1T decision nodes in a soft output Viterbi algorithm ('SOVA') decoder operating with an nT clock signal. An add, compare, select circuit (ACS) of the SOVA generates decision data for decision nodes 1T through nT responsive to each nT clock signal pulse. The decision data is applied to corresponding 1T through nT path equivalency detector circuits to generate 1T through nT path equivalency information for generation of soft output signals corresponding to the 1T through nT decision data.

Methods, apparatus, and systems for determining 1T path equivalency information in an nT implementation of a viterbi decoder

Methods, apparatus, and systems for generating bit-wise reliability information using a soft output Viterbi algorithm ('SOVA') in an nT Viterbi decoder implementation devoid of 1T metric information. At each nT clock pulse 1T equivalent metric values are determined from the current nT metric information. 1T equivalent metric information is determined as values that sum to the corresponding nT metric information. Subtraction is then used to determine state metric difference information from the 1T equivalent metric values. The state metric difference information may then be used to estimate log likelihood ratio information for use in the SOVA algorithm to determine bit-wise reliability information.

Methods, apparatus, and systems for determining 1T state metric differences in an nT implementation of a viterbi decoder

A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

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Loveland, CO, United States of America

Brian K Gutcher