Emc Corporation

Trend Micro Inc.

Hewlett-packard Development Company, L.p.

Brian K Campbell

Ofer Porat

Kendell Alan Chilton

Craig Botkin

Ronald S Stites

Christopher S MacLellan

Miklos A Sandorfi

Gregory S Robidoux

Clayton Alan Curry

Brian D Magnuson

Eric J Bruno

Jane Xu

John K Walton

Daniel Castel

Stephen Lawrence Scaringella

Paul C Wilson

James Creighton Tryhubczak

Adam Peltz

Armen Avakian

Michael Daigle

Man Min (Joshua) Moy

Man Min Moy (Joshua)

Craig D Botkin

Methods and systems are provided for hardware-based pattern matching. In an embodiment, an intrusion-prevention system (IPS) identifies a full match between a subject data word comprising subject-data blocks and a signature data pattern comprising signature-data blocks. The IPS receives the subject data word via a network interface, and thereafter makes a partial-match determination that two or more but less than all of the subject-data blocks respectively match the same number of the signature-data blocks stored in partial-match hardware with respect to both value and position. Thereafter, the IPS makes a full-match determination that all of the subject-data blocks respectively match all of the signature-data blocks stored in the IPS's full-match hardware with respect to both value and position. The IPS then stores an indicator that the full-match determination has been made, and may carry out one or more additional intrusion-prevention responses as well.

Methods and systems for full pattern matching in hardware

According to an example, an intrusion-prevention system may include a network interface to receive a subject data word via a network. The intrusion-prevention system may include hardware to determine whether the subject data word partially matches a signature data pattern, and determine whether the subject data word fully matches the signature data pattern if the subject data word partially matches the signature data pattern.

A method of protecting data during transmission from an ECC protection scheme to a parity protection scheme, including reading a data word and an associated ECC from an upstream device; generating parity for the data word; generating a new ECC from the data word; computing a syndrome of the associated ECC and the new ECC; determining, based on the syndrome, if an error is present in the data word or the associated ECC; correcting a correctable error in the data word; correcting the parity for the data word; and transmitting the corrected data word and the corrected parity for the data word to a downstream device.

Method of and system for protecting data during conversion from an ECC protection scheme to a parity protection scheme

A data transmission system includes a first data transmission device for receiving commands from a host; a second data transmission device for transmitting commands to a memory device; and a crossbar device for receiving commands from the first data transmission device over a first link and transmitting the commands to the second data transmission device over a second link. The crossbar device includes status logic to detect a command transmission error on the first link from the first data transmission device and transmits a retry command to prompt the first data transmission device to retry the transmission of the command over the first link. The second data transmission device reports a transmission error on the second link to the status logic of the crossbar device and the status logic of the crossbar device transmits the retry command to prompt the first data transmission device to retry the transmission of the command over the first link.

Error notification and forced retry in a data storage system

An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.

Method of and system for error checking in a data storage system

A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.

Memory system having daisy chained memory controllers

A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.

Memory system

A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.

System having backplane performance capability selection logic

A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.

Data storage system

A system and method are provided for transferring data appended with a tag indicating whether the transmit data is data allowed to be re-transmitted or inhibited from being re-transmitted to a memory section. A buffer is fed with the transmit data from a data source for transmit data to the memory section. A receiver is receives data from the memory section and checks such received data for errors. Either the transmit data from the data source is coupled to the memory section in absence of a detected error or the data in the buffer is coupled to the memory section when an error has been detected and the data has been tagged with an indication that the transmit data is data allowed to be re-transmitted; selectively.

A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

Data transfer state machines

Data transfer apparatus having upper, lower, middle state machines, with middle state machine arbitrating among lower state machine side requesters including selective assembly/disassembly requests

Growing community of inventors

Cedar Park, TX, United States of America

Brian K Campbell