International Business Machines Corporation

Globalfoundries Inc.

Intel Corporation

Chartered Semiconductor Manufacturing Ltd (Corporation)

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Globalfoundries U.S. Inc.

Advanced Micro Devices Corporation

Globalfoundries U.S. 2 LLC

Brian Joseph Greene

Dureseti Chidambarrao

Yue Liang

Xiaojun Yu

Arvind Kumar

Edward P Maciejewski

Kern Rim

Chun-Yung Sung

Huilong Zhu

William K Henson

Jack Allan Mandelman

Yanfeng Wang

Dan Mihai Mocuta

Judson Robert Holt

Zhijiong Luo

Shreesh Narasimha

Biswajeet Guha

Sunfei Fang

Edward J Nowak

Clement Hsingjen Wann

Haining S Yang

Michael Patrick Chudzik

Jeffrey Bowman Johnson

Qingqing Liang

Gregory Gower Freeman

Manfred Eller

Kangguo Cheng

Tahir Ghani

Dechao Guo

Keith Kwong Hon Wong

Louis Lu-Chen Hsu

Eduard Albert Cartier

Yung Fu Chong

Curtis Tsai

Mahender Kumar

Atsushi Ogino

Devendra K Sadana

Effendi Leobandung

Veeraraghavan S Basker

Keith E Fogel

Shu-Jen Han

Cyril Cabral, Jr

Christian Lavoie

Xiangdong Chen

Rishabh Mehandru

Joel Pereira De Souza

Chandrasekharan Kothandaraman

Unoh Kwon

Rajarao Jammy

Byeong Yeol Kim

Rohit Pal

Daniel J Jaeger

Siddhartha Panda

Troy Lawrence Graves-Abe

Rajesh Rengarajan

Kevin Fischer

Myung-Hee Na

Daniel James Dechene

Matthias Hierlemann

Kevin K Dezfulian

Ja-Hum Ku

Ali Khakifirooz

John J Ellis-Monaghan

Oleg Gluschenkov

Ramachandra Divakaruni

Kevin K Chan

Mukta G Farooq

Ying Di Zhang

Andres Bryant

Chengwen Pei

Chung-Hsun Lin

Herbert Lei Ho

Renee Tong Mo

Robert H Dennard

Dae-Gyu Park

Cory E Weber

Werner A Rausch

Rishikesh Krishnan

Augustin J Hong

Robert Hannon

Zhibin Ren

Nivo Rovedo

Xinlin Wang

Jay William Strane

William Hsu

Keith Howard Tabakman

Yong Meng Lee

Murshed Chowdhury

Thomas Safron Kanarsky

Bingwu Liu

Wenhe Lin

Roman Knoefler

Chung Woh Lai

Sameer Hemchand Jain

Xintuo Dai

Young Way Teh

Daewon Yang

Yue Ke

Kai Zhao

Mickey H Yu

Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

Integrated circuit structures having differentiated channel sizing

Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

Dipole threshold voltage tuning for high voltage transistor stacks

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures

Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Substrate-free integrated circuit structures

Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

Substrate-less electrostatic discharge (ESD) integrated circuit structures

Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

Substrate-less vertical diode integrated circuit structures

Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Gate-all-around integrated circuit structures including varactors

The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Stacked-gate transistors

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Source/drain contact depth control

Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.

Dummy fill scheme for use with passive devices

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

Test structures connected with the lowest metallization levels in an interconnect structure

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

Test structure leveraging the lowest metallization level of an interconnect structure

A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity.

Channel region dopant control in fin field effect transistor

Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

On-chip resistors with direct wiring connections

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Wappingers Falls, NY, United States of America

Brian Joseph Greene