Koninklijke Philips Corporation N.V.

U.S. Philips Corporation

Nxp B.v.

Koninklijke Phillips Electronics N.v.

Brian John Minnis

Paul A Moore

Christopher Brian Marshall

Andrew G Stove

Pascal Philippe

Robert Fifield

Adrian W Payne

Liam M Devlin

Elmar Wagner

An arrangement () and a method for digitally filtering a time-discrete digital signal, wherein the signal is transformed to the frequency domain using discrete Fourier transformation (), the signal is filtered in the frequency domain (), wherein a filter response can be adapted in real time as required to respond to changes in the interference environment, and the filtered signal is transformed back to the time domain using inverse discrete Fourier transformation () to create an output signal, and wherein bin frequencies of said signal in the frequency domain are translated by a real amount and the sampling rate of the output signal is changed by a real factor.

Fractional frequency and sampling-rate change in the frequency domain

A transmitter has a power amplifier () to amplify an input signal having amplitude modulation, a supply voltage controller () to control a supply voltage of the power amplifier () according to the envelope, a sensor (R) for sensing a modulation of a current drawn by the power amplifier (), a delay detector () for detecting a delay of the controlled supply voltage relative to the sensed current, and a delay adjuster () for compensating the relative delay according to the detected delay. By sensing a current drawn, the delay detected can include any delay contributed by the power amplifier () up to that point, and yet avoid the more complex circuitry needed to derive the delay from an output of the power amplifier. Thus the distortion and out of band emissions caused by differential delays can be reduced more effectively.

RF transmitter with compensation of differential path delay

A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator () for deriving a demodulated bit rate signal, means () for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means () for selecting the threshold value for comparison with the current bit signal (S) in response to a sequence of N bits (where N is at least 2) (B, B) received prior to the current bit (B) and means () for using the current bit to update the selected threshold value. Also disclosed is a method of dc offset correction.

Receiver having a variable threshold slicer stage and a method of updating the threshold levels of the slicer stage

A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter () for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter () for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter () is terminated, the other (I) is digitised by a non-complex ADC (), then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter () are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs () is possible, thereby avoiding duplication of circuitry and providing significant power savings.

Radio receiver

A radio receiver configurable to operate in either a low-IF or a zero-IF mode comprises a quadrature down-converter () for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter () for performing image rejection filtering. One of the outputs (Q) of the filter () is terminated, the other (I) is passed to a non-complex ADC (). The output from the ADC is processed digitally then a quadrature signal generator () generates quadrature-related IF signals which are passed to a down-converter () for conversion to baseband signals. By enabling analogue-to-digital conversion and channel filtering to be performed at IF on non-complex signals, significant power savings are possible. Further, the flexibility of the receiver is enhanced, enabling it to operate efficiently in both low-IF and zero-IF modes.

A polyphase receiver comprises an RF front end (to) for receiving a wanted data signal modulated on a carrier signal and for producing quadrature related low IF signals, an image rejection filter formed by a polyphase filter () for filtering the quadrature related low IF signals, soft limiting means () for compressing the dynamic range of the filtered quadrature related IF signals and a signal demodulator () for recovering the data signal. The soft limiting means () has a characteristic which is substantially linear at signal levels 10 dB below a predetermined minimum wanted signal level, moves into compression for higher signal levels and hard limits at substantially 10 dB above the desired receiver sensitivity which avoids degrading the sensitivity of the receiver.

Polyphase receivers

A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter is terminated, the other (I) is digitised by a non-complex ADC then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs is possible, thereby avoiding duplication of circuitry and providing significant power savings.

A radio transmitter for multi-standard mobile communication systems has two stages of frequency up-conversion, the first being a digital process generating a variable IF and the second being an analogue conversion using a fixed frequency local oscillator, which alleviates the need for RF filtering after the final stage of power amplification. The IF frequency band is symmetrical about zero frequency and thus includes negative frequencies.

Radio transmitter

A circuit arrangement for providing impedance translation filtering comprises a first path and a second path. In a base band variant the first path is a feed forward path which comprises first and second series connected transconductance gain stages ( ), and the second path is a feedback which comprises third and fourth transconductance gain stages ( ), each having an inverting output. An output of the first gain stage is coupled to an input of the fourth gain stage. In operation, the impedance presented at its output determines the impedance presented at an input of the circuit arrangement.

Circuit arrangement providing impedance translation filtering

A transmitter has a phase modulator and a phase locked loop that has a relatively high powered voltage controlled oscillator. The phase locked loop has a phase sensitive detector for comparing a phase comparison frequency derived from the voltage controlled oscillator output with a phase modulated intermediate frequency carrier derived from the phase modulator. The phase modulator has a reference frequency source, means for deriving four quadrature phase components of the reference frequency produced by the source and phase selection means controlled by complex modulation means for deriving the phase modulated intermediate frequency carrier by random interpolation between the four quadrature components.

Transmitter with a phase modulator and a phase locked loop

A fractional-N frequency synthesizer for use in a transmitter for transmitting TDMA signals, comprises a fourth order sigma-delta modulator( ) having an input for digitized signals, a FIR filter( ) having taps coupled to an output of the sigma-delta modulator, the FIR filter ( ) serving to increase the number of states on its output by one over the number of states on its input which is connected to an output of the sigma-delta modulator, and a phase locked loop(PLL) including a frequency divider( ) with an incremental ratio of 0.5 and having a control input coupled to an output of the FIR filter. The frequency divider ( ) by having an incremental ratio of 0.5 enables the PLL to have a reference oscillator( ) operating at half the sampling frequency of the sigma-delta modulator( ). The frequency synthesizer as a consequence has been found to give a 12 dB improvement in noise level and also continuous tuning can be achieved because the successive groups of three half ratios adjacent tuning ranges made possible by using overlap.

Fractional-N frequency synthesizer

A transmitter in which a complex low IF digitised signal is applied in quadrature to a complex phase comparator together with a digitised frequency down-converted version of an analogue signal produced by a transmitter VCO. The low IF digitised signal serves as a reference against which the digitised frequency down-converted version of the transmitter VCO is compared. The output of the complex phase comparator is converted to an analogue signal which is applied as a control signal to the transmitter VCO. An analogue embodiment of the transmitter which uses zero-IF signals is also disclosed.

Transmitter with complex phase comparator

A microwave amplifier circuit has input and output coupling circuits (21 and 22) designed on quite different matching principles to obtain a circuit compactness similar to a reactively-matched amplifier and cascadable electrical characteristics similar to a distributed amplifier. The input coupling circuit (21) is formed as a bandpass filter network (7a, 7b, 7c, 17a, 17b, 9) supporting a travelling wave to which the amplifying device (3) is capactively connected. This input network (21) terminates in a resistor (9) in which the travelling wave is dissipated. The output coupling circuit (22) is a reactively matched circuit (8a, 8b, 18a, 18b) which also has a bandpass characteristic. By making the input network (21) bandpass (instead of low pass) a large amplifying device (3) can be used, without reducing line impedance and gain.

Compact cascadable microwave amplifier circuits

A variable bi-phase modulator circuit for microwave signals includes a quadrature power divider (1) having signal input and output ports (2 and 3) and two control ports (4 and 5), and two variable resistors each having an input port (11). Each of the two variable resistors includes first and second microwave field-effect transistors (F1 and F2), the drains of which are coupled together via an intermediate resistor (R). These resistors can be formed using microwave monolithic integrated circuit technology and can have very good impedance characteristics. The input port (11) of the variable resistor has a connection to the intermediate resistor (R) and to the drain of the first transistor (F2). Each transistor is connected with zero dc bias between its source and drain and has a channel resistance which changes with change in gate voltage (VG1, VG2). A shunt stub (L1, L2) is connected to the drain of each transistor (F1, F2) to at least partially compensate at the frequency of operation of the transistor for the source to drain capacitance and for shifts in reference plane due to changes in the gate voltage of each transistor.

Variable bi-phase modulator circuits and variable resistors for

A CW radar comprises a substantially continuously operable transmitter (10) and receiver (16,18,20), signal operating means (12,14) for radiating the transmitter signal and for receiving at least the return signal and a reflected power canceller (RPC) circuit (26, 28 and 30) for cancelling leakage signals in a signal path from the signal operating means to the receiver. The receiver front end comprises quadrature related mixers (18,20) which supply intermediate frequency signals (I.sub.1 and Q.sub.1) to a low frequency control loop (32, 34, 36) which supplies at least a pair of control signals (I.sub.c, Q.sub.c) to a four quadrant vector modulator (28) in the RPC circuit. In order to be able to optimize the cancellation of phase as well as amplitude, the control circuit loop includes means for suynthesizing control vectors (I.sub.1 -I.sub.1, Q.sub.1 and -Q.sub.1) from the outputs of the quadrature related mixers (18,20). Selecting means selects a pair of quadrature related control vectors from those control vectors synthesized on the basis of minimizing leakage in the outputs of the quadrature related mixers (18,20). The selected control vectors (I.sub.c, Q.sub.c) are applied to the four quadrant vector modulator (28) which preferably comprises a pair of analogue driven biphase modulators (56,58- FIG. 4 (not shown)). In an alternative embodiment (FIG. 7) the four quadrant vector modulator comprises four voltage controlled attenuators to which respective control vectors (I.sub.c, -I.sub.c, Q.sub.c and -Q.sub.c).

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Crawley, United Kingdom

Brian John Minnis