International Business Machines Corporation

Qualcomm Incorporated

Brian Joel Schuh

Robert Michael Bunce

Mark R Bilak

Steven C Parker

Hayden C Cranford, Jr

Vernon Roberts Norman

Gareth John Nicholls

Juan Antonio Carballo

Louis L Hsu

Christos J Georgiou

Michael Raymond Trombley

Timothy Michael Kemp

Carrie Ellen Cox

Patrick H Buffet

Charles S Chiu

Louis T Fasano

Kevin G Kramer

Thomas J Bardsley

Jon David Garlett

Vinay V Shah

Christopher Philip Parker

Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.

Clock data recovery broadcast for multi-lane SerDes

An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Dynamic memory allocation between inbound and outbound buffers in a protocol handler

A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

Altering power consumption in communication links based on measured noise

A networked conferencing system is described wherein multiple moderation of conferences is accommodated by permitting a conference moderator to designate one ore more alternate conference moderators. Each alternate moderator has access to at least a subset of conference moderation functions, thereby permitting any alternate moderator to take at least partial control of conference proceedings in the absence of the 'main' or 'primary' moderator.

Multiple moderation for networked conferences

A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.

Apparatus and method to reduce signal cross-talk

A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fiber Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.

Inbound data stream controller with pre-recognition of frame sequence

An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.

Integrated real-time data tracing with low pin count output

A network system in which data is transferred through a bypass circuit which extends between the ends of a branch and becomes active when all the disk drives in the branch are inactivate, rather than the data being transferred through bypass circuits individually associated with the disk drives and which become active when the disk drives are inactive.

Network system having a secondary disk drive bypass circuit activated

An I/O interface for an integrated circuit (IC) is described that has a reduced number of I/O pins dedicated to providing control signals to or status information from the IC. In one embodiment, the IC comprises a plurality of input pins connected to logic for receiving and processing input data. The input pins have an input bandwidth greater than the logic's processing rate. If data and control signals are multiplexed onto the same input pin, the excess input pin bandwidth may used to transfer control signals into a plurality of latches within the IC. The I/O interface outputs a select signal that designates when an external device should drive the input pins with either data or control signals. In a specific embodiment, the logic comprises a parallel to serial converter and the control signal select conversion speed or encoding options. In another embodiment, the IC comprises a plurality of output pins connected to the output of a selector. Status latches and logic for outputting processed data drive the selector's inputs. The IC outputs a select signal that allows an external device to determine when the output pins are carrying processed data versus status information and thus demultiplex the signals. In a specific embodiment, the logic is a serial to parallel converter. Finally, both the input and output pin embodiments may used together in a single IC.

Growing community of inventors

Apex, NC, United States of America

Brian Joel Schuh