Integrated Device Technology, Inc.

Durel Corporation

Brian Jeffrey Buell

Song Gao

Robert Allen Kimball

Katherine T Blinick

Grady M Wood

Pengfei Hu

Benedykt Mika

Li Tao

Chen-Wei Huang

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

Fractional divider using a calibrated digital-to-time converter

A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC) signal during an active mode of operation. The phase correction circuit further generates an FD output signal in response to the periodic MMD output signal and a preliminary multi-bit phase correction control (PPCC) signal during a calibration mode of operation. A control circuit is provided, which generates the modulus control signal, the PPCC signal and the CPCC signal during the active mode of operation.

Self-calibrating fractional divider circuits

A digital filter for a frequency synthesizer (e.g., PLL, UFT) may include an analog-to-digital (ADC) converter, which is responsive to a control voltage at an input thereof, and a digital-to-analog (DAC) converter, which has an input responsive to a signal generated at an output of the ADC. An impedance element is provided between the DAC and ADC. The impedance element has real and reactive components, a first current carrying terminal electrically coupled to an output of the DAC and a second current carrying terminal electrically coupled to the input of the ADC. The impedance element can include a resistor and a capacitor, which are electrically connected in parallel. A gain device, such as a programmable multiplier, may also be provided, which has an input responsive to the signal generated at the output of the ADC and an output electrically coupled to the input of the DAC.

Digital filter for phase-locked loop integrated circuits

A PLL includes a fractional divider to generate a periodic PLL output signal in response to REF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFand a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.

Fractional divider based phase locked loops with digital noise cancellation

An apparatus includes a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and a control circuit configured to generate a measure of a difference between the PLL output signal and an input clock signal at a control output thereof. The apparatus further includes a dynamic range shifter circuit coupling the control output of the control circuit to a control input (e.g., a feedback divider control input) of the PLL circuit and configured to shift a dynamic range of the control output of the control circuit with respect to a dynamic range of the control input of the PLL circuit. The apparatus may be implemented with an oscillator, such as a MEMs oscillator, in a single chip.

Clock generation circuits using jitter attenuation control circuits with dynamic range shifting

Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.

Fractional-N dividers having divider modulation circuits therein with segmented accumulators

An extended range voltage controller oscillator (VCO) circuit for use in a phase-locked loop (PLL) circuit is provided. The VCO circuit includes two additional pairs of varactors which are used to extend the range of the VCO circuit around its center frequency.

VCO digital range selection

A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and the gate of the first bias switching NMOS is coupled to the output of the first logic gate. The second bias switching NMOS is electrically coupled between the source of the fourth NMOS and ground, and the gate of the second bias switching NMOS is coupled to the output of the second logic gate.

Low power logic output buffer

An inverter for driving an EL lamp is tapped to provide voltage or current for driving one or more EL lamps and an LCD. In accordance with one aspect of the invention, one side of the pump inductor is tapped for a voltage that drives the LCD.

Inverter for driving EL lamp and liquid crystal display

An inverter for driving an EL lamp is tapped to provide voltage or current for driving one or more EL lamps, LEDs, and an LCD. In accordance with one aspect of the invention, one side of the pump inductor is tapped for a voltage that drives one or more LEDs and the LCD. In accordance with another aspect of the invention, the LEDs are in series with a storage capacitor and are driven by the current pulses to the storage capacitor.

Inverter for driving EL lamp and light emitting diodes

A driver for an EL lamp includes a voltage detector coupled to the lamp for monitoring the voltage across the lamp and providing an indication of when the lamp is substantially discharged.

EL driver with lamp discharge monitor

A driver for an EL lamp includes a source of high voltage coupled to a first voltage rail and a second voltage rail and a transistor bridge output coupled to the rails, wherein the bridge output has no current mirrors for the high side transistors in the bridge output.

EL driver with low side current mirrors

An inverter for driving an EL lamp includes a half-bridge output. The inverter can be implemented in junction isolation processes, among others, on smaller die than in the prior art in a package with a lower pin count than known circuits of the same functionality.

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Gilbert, AZ, United States of America

Brian Jeffrey Buell