Virata Corporation

Conexant Systems, Inc.

Globespan Virata Corporation

Conexant, Inc.

Brooktree Broadband Holding, Inc.

Brooktree Broadband Holdings, Inc.

Brian James Knight

Mark Justin Moore

David Milway

David Greaves

Fash Nowashdi

David Russell Milway

Chris Holland

Timothy John Chick

A method is described that comprises suspending a currently executing thread at a periodic time interval, calculating a next time slot during which the currently executing thread is to resume execution, appending the suspended thread to a queue of threads scheduled for execution at the calculated time slot, and updating an index value of a pointer index to a next sequential non-empty time slot, where the pointer index references time slots within an array of time slots, and where each of the plurality of time slots corresponds to a timeslice during which CPU resources are allocated to a particular thread. The method further comprises removing any contents of the indexed non-empty time slot and appending the removed contents to an array of threads requesting immediate CPU resource allocation and activating the thread at the top of the array of threads requesting immediate CPU resource allocation as a currently running thread.

System and method for scheduling threads requesting immediate CPU resource in the indexed time slot

The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

System and method for packet transmission from fragmented buffer

A circular array structure is maintained having multiple time slots, where each time slot corresponds to a timeslice during which CPU resources are allocated to a particular thread. The time slots in the circular array include a queue of threads scheduled for execution during that time slot. A pointer index and an array of threads requesting immediate CPU resource allocation are maintained. A currently executing thread is suspended, and a next time slot during which the currently executing thread should resume execution is calculated. The suspended currently executing thread is appended to the queue of threads scheduled for execution at the calculated time slot. The pointer index is undated to point to the identified next sequential non-empty time slot. Any contents of the indexed time slot is appended to the array of threads requesting immediate CPU resource allocation. The thread at the top of the array is removed and activated.

System and method for scheduling thread execution

One embodiment of a method for switching ATM cells using Early Packet Discard and Partial Packet Discard is provided. Initially, a first cell of an AAL5 packet is received at an input port. Next, it is determined whether there is likely to be enough buffering available to handle the whole packet (i.e., up to 64 Kbytes). If it is determined that sufficient buffering is unlikely to be available, the entire packet is discarded. If it is determined that sufficient buffering exists, the cell is received and buffered for subsequent transmission. Next it is determined whether the flow's buffer is filled at any time after initial transmission of a AAL5 cell but before reception of the final cell. If such a state is determined, the current cell is discarded and a flag is set in the flow structure so that subsequent cells of the same packet, except the last, will also be discarded.

System and method for switching asynchronous transfer mode cells

A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reassembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

DMA scheduling mechanism

A method and apparatus for controlling memory access in a system where at least a first and a second processor each share a common memory. The first processor has a write buffer, in which it stores words prior to writing them in the common memory, and a cache for receiving words from the common memory. The common memory is mapped twice into the address space of the first processor so that, in a first mapping, the first processor accesses the common memory directly and in a second mapping, the cache is enabled. The common memory can therefore be directly accessed with the first processor and the second processor when they share data that is read from or written into the common memory. The cache is accessed with the first processor in the second mapping for reading and writing data local to the first processor. Information written into the write buffer is tagged and the tagged information is flushed into the shared memory before the shared memory can be accessed by the second processor.

Method and apparatus for controlling shared memory access

A switching device for switching ATM cells from a plurality of network input links to a plurality of network output links comprises a plurality of ports containing line interfaces and input and output buffers, a hardware switch controller, a microprocessor, and memory for storing routing tables and system software. All these elements are interconnected via a processor bus, and additionally, the ports are interconnected by a separate switching bus. The switch controller employs hash-based routing table indexing to route cells from selected input ports to appropriate output ports according to the cells' header information. Switch requests generated by incoming cells are arbitrated using a token bus allocation scheme. The majority of cells are switched almost entirely in hardware, but the microprocessor can assume control of the switching architecture to resolve exception conditions and to perform special processing on selected virtual circuits. Two output buffers per port are provided; one for high-priority cell, another for lower priority cells. Additionally, a common overflow buffer is provided to temporarily store cells intended for output buffers momentarily full.

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Cambridge, United Kingdom

Brian James Knight