Qualcomm Incorporated

Second Sound, LLC

Qualcomm Atheros Inc.

Brian James Kaczynski

Paul J Husted

David Kuochieh Su

Michael Peter Mack

Srenik Suresh Mehta

Soner Ozgur

Richard Chang

Emmanouil Terrovitis

MeeLan Lee

Hyunsik Park

Sang-Min Lee

Tomas O'Sullivan

Hirad Samavati

Sotirios Limotyrakis

Cristian Marcu

Noam Lavi

Alireza Kheirkhahi

Methods and digital circuits provide frequency correction to frequency synthesizers. Dual switched-capacitor voltage detectors connected to an input signal periodically sample the voltage of the input signal, and then determine a fundamental frequency of the input signal from the output of the dual switched-capacitor voltage detectors. The sample period of the dual switched-capacitor voltage detectors is proportional to a time period between a previous pair of voltage peaks detected in the input signal, thereby eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation without causing unwanted sluggishness in the transient response of the frequency detection process. The time period between the previous pair of detected voltage peaks is used to create a decay signal that initiates a capacitor decay time for each voltage detector. Two additional digital methods of extracting the fundamental frequency as well as an envelope of an analog audio signal are also described, one utilizing a sliding sample rate, and the other utilizing a fixed sample rate.

Fundamental frequency detection using peak detectors with frequency-controlled decay time

Methods and systems including music synthesizers for synchronous sampling of analog signals are disclosed. A music synthesizer can include an adaptive low-pass filter, a synchronous sample clock generator, a digital signal processor, an analog-to-digital converter, and a digital-to-analog converter. The synchronous sample clock generator creates a synchronous sample clock signal using a filtered audio signal, as well as an 'up' pulse and a 'down' pulse, all of which are utilized by the digital signal processor to perform operations on the audio signal. The digital signal processor generates a clean sample clock for resampling the original audio signal to the synchronous sample clock rate.

Synchronous sampling of analog signals

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

Apparatus for tracking the fundamental frequency of a signal with harmonic components stronger than the fundamental

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again.

Fast-locking frequency synthesizer

A variable attenuator can be used with high-voltage radio-frequency signals. The attenuator can provide wide dynamic range with little loss at the lowest attenuation level. The attenuator may be implemented in digital integrated circuit processes and occupies small integrated circuit area. Additionally, the use of circuit elements external to the SoC may be reduced. The attenuator uses multiple attenuator cells connected in parallel to an RF input and RF output. The attenuator cells use capacitive dividers with pair of capacitors laid out in the same integrated circuit area. The capacitors are also laid out so that the RF input shields the RF output from ground to avoid parasitic capacitance on the RF output.

High-voltage radio-frequency attenuator

A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Systems and methods for frequency synthesis to improve coexistence

A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

Hybrid successive approximation analog-to-digital converter

Controlling power consumption in a wireless device. The wireless device may include first wireless protocol circuitry. The first wireless protocol circuitry may be configured to receive and process first signals according to a first wireless protocol. The wireless device may include a power controller coupled to the first wireless protocol circuitry. The power controller may be configured to control power consumption of elements of the first wireless protocol circuitry based on a current state. More specifically, in response to the first wireless protocol circuitry being in a listening state, the power controller may be configured to lower power consumption of one or more first elements of the first wireless protocol circuitry. Additionally, in response to the first wireless protocol circuitry being in a receiving state, the power controller may be configured to return power consumption of the one or more first elements to a higher power level.

Power management of wireless protocol circuitry based on current state

A fast settling frequency synthesizer is disclosed. The particular capacitor to frequency relationship in the band of operation is first determined. The calculation can be performed by determining the capacitor to frequency relationship at two points and calculating the slope. Once these parameters are known, then, for any change in frequency due to a channel hop, the appropriate capacitor value can be determined.

Method and apparatus for multi-point calibration for synthesizing varying frequency signals

A transceiver for use in a wireless device. The transceiver may include a receive portion for receiving an input RF signal. The receive portion may include at least one receive filter which may include a first filter. The transceiver may also include a transmit portion for transmitting an output RF signal. The transmit portion may include at least one transmit filter, which may include the first filter used in the receive portion. The transceiver may further include a plurality of switches, which may include a first switch coupled to an input of the first filter and a second switch coupled to an output of the first filter. The plurality of switches may be configurable to enable use of the first filter in the receive portion for receiving the input RF signal and use of the first filter in the transmit portion for transmitting the output RF signal.

Wireless transceiver using shared filters for receive, transmit and calibration modes

A VCO comprises an LC tank circuit coupled to a plurality of cross-coupled transistor devices. A first resonance frequency of a waveform output of the VCO is dependent upon the values of a first capacitor and a first inductor of the LC tank. The VCO further comprises a first series LC resonator comprising a second capacitor and a second inductor in parallel to the first capacitor and the first inductor. The values of the second capacitor and second inductor are selected to produce a second resonance frequency that is a third harmonic of the first resonance frequency, thereby increasing a slope of the voltage controlled oscillator output. The increased slope reduces phase noise, which leads to improved signal-to-noise ratio.

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Cracow, Poland

Brian James Kaczynski