Google Inc.

Brian James Burkett

Rami Barends

Ofer Naaman

Anthony Edward Megrant

Theodore Charles White

Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Josephson junctions with reduced stray inductance

A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.

Reducing junction resistance variation in two-step deposition processes

A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

Compensating deposition non-uniformities in circuit elements

A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (), forming a first resist layer () on the dielectric substrate, forming a second resist layer () on the first resist layer, and forming a third resist layer () on the second resist layer. The first resist layer includes a first opening () extending through a thickness of the first resist layer, the second resist layer includes a second opening () aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening () aligned over the second opening and extending through a thickness of the third resist layer.

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Santa Barbara, CA, United States of America

Brian James Burkett