Qualcomm Incorporated

Brian J Salsbery

Norman S Gargash

Bohuslav Rychlik

Sumit Sur

Steven S Thomson

Ali Iranli

Robert A Glenn

Reza Shahidi

Ajith Tom Payyappilly

Andrew James Frantz

Alex Kuang-Hsuan Tu

Christopher L Medrano

Sean Sweeney

Praveen Kumar Chidambaram

Christopher A Barrett

Robert Nicholson Gibson

Navid Farazmand

Yizheng Zhou

Mark D Guzzi

Purandar Mukundan

Xiaodong Chen

Chris Barrett

Norman S Garash

Jeremy Gebben

Lucille Garwood Sylvester

Andrew J Frantz

Sean D Sweeney

Example implementations and techniques are described in which a processor uses a dynamic adjustment algorithm, including algorithms based on performance and energy models, to readjust frequency settings for a graphics processing unit (GPU), and independently for a system memory or for a system memory bus, to an optimal level for meeting sustained performance requirements with the low level of power consumption.

Energy aware dynamic adjustment algorithm

A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.

System and method for controlling central processing unit power based on inferred workload parallelism

A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time tto t. A timer is set to trigger a forced power collapse ('FPC') that removes all power to the processor from time tto time t. At time t, the processor may be awakened such that it can resume processing at the full frequency. Advantageously, during the FPC, no leakage power ('P') is consumed by the processor between tand t. The result is that the processor averages the same processing efficiency over time tto tas it otherwise would have if a reduced frequency had been provided to it. However, because no Pwas consumed during the FPC, the generation of heat between time tand tthat is related to Pis avoided.

Method and system for reducing thermal load by forced power collapse

The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter.

Dynamic low power mode implementation for computing devices

Apparatus and methods are disclosed for power optimization in a wireless device. The apparatus and methods effect monitoring the amount of data stored in a data buffer that buffers data input to and data output from a processor. Dependent on the amount of data stored in the buffers parameters of a control function, such as a Dynamic Clock and Voltage Scaling (DCVS) function are modified based on the amount of data stored in the data buffer. By modifying or pre-empting the parameters of the control function, which controls at least processor frequency, the processor can process applications more dynamically over default parameter settings, especially in situations where one or more real-time activities having strict time constraints for completion are being handled by the processor as evinced by increased buffer depth. As a result, power usage is further optimized as the control function is more responsive to processing conditions.

Apparatus and methods for optimizing power consumption in a wireless device

A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.

System and method for controlling central processing unit power with reduced frequency oscillations

A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on tempature

A method of executing a dynamic clock and voltage scaling (DCVS) algorithm in a central processing unit (CPU) is disclosed and may include monitoring CPU activity and determining whether a workload is designated as a special workload when the workload is added to the CPU activity.

User activity response dynamic frequency scaling processor power management system and method

System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature

A method of utilizing a node power architecture (NPA) system, the method includes receiving a request to create a client, determining whether a resource is compatible with the request, and returning a client handle when the resource is compatible with the request.

System and method of controlling power in an electronic device

A method of tuning a dynamic clock and voltage switching algorithm is disclosed and may include setting a default responsivity, determining whether a workload is registering after the workload is added, assigning a unique identifier to the workload if the workload is registering, and receiving a required responsivity from the workload.

System and method of tuning a dynamic clock and voltage switching algorithm based on workload requests

A method and system for maximizing a quality of service ('QoS') level in a portable computing device ('PCD') by preempting the generation of thermal energy in excess of a threshold are disclosed. The method includes receiving a workload request for a processing component within the PCD. A processing component is selected for allocation of the workload based on thermal factors associated with the processing component. Thermal factors may comprise data indicative of real-time thermal energy generation near the processing component, predictive data derived from known characteristics of heat producing components that are physically proximate to the processing component, queued workload burdens for the processing component, etc. A processing component is selected for allocation of the workload based on the thermal factors. By leveraging the thermal factors to allocate workloads, thermal generation can be proactively managed such that reliance on reactive thermal mitigation techniques, which negatively impact QoS, can be reduced.

Method and system for preempting thermal load by proactive load steering

A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.

System and method for asynchronously and independently controlling core clocks in a multicore central processing unit

System and method of dynamic clock and voltage scaling for workload based power management of a wireless mobile device

A method of dynamically controlling power within a multicore central processing unit is disclosed and includes executing a plurality of virtual cores, virtually executing one or more tasks, one or more threads, or a combination thereof at the virtual cores, and physically executing one or more tasks, one or more threads, or a combination thereof at a zeroth physical core. The method may further include receiving a degree of parallelism in a workload of a plurality of virtual cores and determining whether the degree of parallelism in the workload of the virtual cores is equal to a first wake condition.

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Boulder, CO, United States of America

Brian J Salsbery