Lucent Technologies Inc.

Agere Systems Inc.

Brian J Petryna

Zhigang Ma

Oceager P Yee

Dale Harvey Nelson

Wenzhe Luo

Horng-Dar Lin

Kouros Azimi

Gordana Pavlovic

Alexander Anesko

A single coder/decoder shared among several multiprocessors in a digital signal processing system through time-division multiplexing between multiple processors to enhance signal processing capabilities by assigning different digital-to-analog channels to different processors for digital-to-analog conversion, while allowing all processors to operate on the same analog-to-digital data for analog-to-digital conversion, thereby resulting in chip area reduction and power consumption saving.

Shared CODEC in multiprocessor systems

A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.

Multifunction reset for mixed-signal integrated circuits

A new memory cell design having differential and dedicated read and write ports is disclosed. The memory cell utilizes separate write and read bit lines. The read bit lines are pre-charged to a first level. A grounding transistor is provided between the circuitry containing the cell's contents and the read bit lines such that the contents of the cell are isolated from the read bit lines. The grounding transistor is activated and deactivated by the data within the cell. The activation and deactivation of the grounding transistor causes the pre-charged bit lines to be pulled-down to a second level or to remain at the first level to accurately reflect the contents of the cell. Since the circuitry containing the contents of the cell is isolated from the read bit lines, a read operation on the cell will not interfere with an in progress write operation and thus, destruction of the cell's contents is prevented. In addition, the isolation prevents bit line coupling.

Message box memory cell for two-side asynchronous access

A programmable motion estimator having a memory and processing element array that implement a dual addressing scheme and a block rotating scheme that work together to perform block difference calculations required in video encoder subsystems to provide motion estimation with less processing power without comprising video quality.

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Lebanon, NJ, United States of America

Brian J Petryna