Inmos Limited

Other

Brian J Parsons

Peter William Thompson

Michael David May

Christopher Paul Walker

Richard M Forsyth

Saeid Azmoodeh

Chistopher P Walker

Christopher P Walker

Peter Malcolm Boffey

Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.

System for grouping instructions for multiple issue using plural

A computer device comprises a processor for executing a plurality of concurrent processes each comprising a sequence of instructions, memory including RAM, at least one message link having input and output pins for connection to a device separate from said computer device and for transmitting message packets sequentially between the computer device and said separate device, and communication control circuitry coupled to said processor, to said memory, and to said message link. The memory provides a plurality of addressable virtual communication links. The communication control circuitry is operable:

Apparatus providing addressable storage locations as virtual links and

A communications device, particularly but not exclusively for use with a routing circuit, transmits and receives message packets. An output buffer converts data and flow-control information into a plurality of bit sequences and transmits them at a predetermined frequency. An input buffer decodes informing sequences into data items and flow control information. The input buffer can store the data items and count them and transmit flow control information to the output buffer.

Data flow control mechanism utilizing low level flow control codes

A method of routing messages through a network is described in which a message packet is dispatched with two node indicators through the network including a succession of routing switches. When the message packet reaches a routing switch identified by the first node indicator, that routing switch deletes the first node indicator and the second node indicator is then used to route the message packet through the network.

Message encoding

A method of encoding data for transmission between computer devices is disclosed in which data is encoded into a plurality of sequences, each sequence containing an equal number of ones and zeros and being of a predetermined bit length. There is a finite set of the permutations of equal numbers of ones and zeros in that predetermined bit length. One subset of the finite set is selected for use as data codes and a second subset is selected for use as control codes.

Message encoding which utilizes control codes and data codes

A routing switch includes an input for receiving serial packets from a source node in a computer network, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the packet. The header reading circuitry is coupled to the switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion. There is also provided a computer network, having a plurality of computer devices and at least one routing switch, and a method of routing messages through such a network.

Message routing

A routing switch includes an input for receiving serial packets from a source node in a computer network, a plurality of outputs, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the packet. The switch also has a random header generator which produces header portions generated at random which are then read by the header reading circuitry. The header reading circuitry is coupled to the switch circuitry to connect to said input one of said outputs in dependence on said random header. The random header portion is then discarded at the routing switch identified thereby to reveal the original header.

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Bristol, United Kingdom

Brian J Parsons